Senior FPGA Engineer — Hybrid (Barcelona)

Script & Dot; Barcelona; Híbrido; EUR 60.000 - 100.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Hybrid work Barcelona

6-month contract

Potential for extension

Descripción de la vacante

Script & Dot in Barcelona is seeking a Senior FPGA Development Engineer for a hybrid 6-month contract. You will design, implement and validate FPGA functionality with cross-disciplinary engineers in an international team.

Key tasks include SystemVerilog development, lifecycle ownership from implementation to hardware validation, and optimizing designs for timing and reliability. Collaboration with software and hardware teams is essential.

Formación

• Strong commercial FPGA development experience.
• RTL development using SystemVerilog, Verilog or VHDL.
• Experience with Xilinx/AMD FPGA platforms and Vivado or comparable toolchains.
• FPGA implementation, simulation and timing closure.
• RTL development within complex FPGA-based systems.
• Good understanding of digital design, clock-domain crossing and interface design.
• Experience integrating FPGA with software and hardware teams.
• Familiarity with Git and collaborative development environments.

Responsabilidades

• Developing and enhancing FPGA functionality using SystemVerilog.
• Working across the full FPGA development lifecycle from implementation to verification and hardware validation.
• Optimising FPGA designs for performance, reliability and timing.
• Debugging complex FPGA issues spanning FPGA, embedded software and hardware.
• Integrating FPGA designs into larger hardware and software systems.
• Collaborating with engineers across multiple disciplines to deliver production-quality solutions.

Conocimientos

SystemVerilog

Verilog

VHDL

RTL development

Digital design principles

Git

Collaboration across disciplines

Herramientas

Vivado

Descripción del empleo

Script & Dot in Barcelona is seeking a Senior FPGA Development Engineer for a hybrid 6-month contract. You will design, implement and validate FPGA functionality with cross-disciplinary engineers in an international team.

Key tasks include SystemVerilog development, lifecycle ownership from implementation to hardware validation, and optimizing designs for timing and reliability. Collaboration with software and hardware teams is essential.