DMS Verification Engineer

Joinimagine; Valencia; Presencial; EUR 45.000 - 70.000; Jornada completa

Descripción de la vacante

Bosch in Valencia is seeking an experienced DMS Verification Engineer to join our engineering team. You will collaborate with system architects and designers to develop comprehensive verification plans for mixed-signal SoCs and lead verification activities.

You will drive verification strategy, oversee regressions, and ensure coverage, while mentoring across multi-site teams. Fluency in English and EU work authorization are required, with a strong focus on reliability and innovation.

Formación

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Telecommunications, Computer Science, or a related field.
• Proven experience in developing validation plans, analyzing test results, and debugging failures at RTL, gate, and schematic levels.
• Strong working knowledge of SystemVerilog/Verilog and UVM.
• Experience setting up, running, and debugging Gate-Level Simulations (GLS).
• Good understanding of DSP techniques and analog schematics.
• Strong problem‑solving, communication, and teamwork skills.
• Professional working proficiency in English (C1 level minimum).
• Valid work authorization for the European Union is required.

Responsabilidades

• Drive specification reviews to generate initial verification plans using Vmanager.
• Define verification strategies, including optimal partitioning between DMS and DV, and model versus schematic equivalence.
• Plan and manage resources, schedules, and progress tracking, identifying and addressing potential showstoppers.
• Implement verification plans, run regressions, and track functional and code coverage.
• Verify the accuracy and performance of behavioral models against circuit-level simulations and measurements.
• Perform root-cause analysis and debug issues down to RTL, gate, and schematic levels.
• Maintain and improve functional verification infrastructure, flows, and UVM methodologies.
• Provide technical leadership, mentorship, and support across multi‑site engineering teams.

Conocimientos

SystemVerilog

UVM

GLS

DSP techniques

RTL debugging

Schematic debugging

English Proficiency

Teamwork

Problem solving

Educación

Electrical/Electronic Engineering

Herramientas

Vmanager

Descripción del empleo

Company Description

At Bosch, we shape the future with high-quality technologies and services that inspire enthusiasm and improve people’s lives . Driven by our ethos \"Invented for life,\" the Bosch Group is a leading global supplier of technology and services, operating across four primary business sectors: Mobility, Industrial Technology, Consumer Goods, and Energy and Building Technology.

As a values-driven organization owned largely by the charitable Robert Bosch Stiftung, we focus on sustainable, long-term growth, purpose-driven innovation, and creating a working environment where diversity, collaboration, and personal development thrive . Whether you are developing cutting-edge software, advancing smart manufacturing, or engineering sustainable energy solutions, Bosch offers you the opportunity to make a meaningful global impact.

Job Description

We are seeking an experienced DMS (Directed Mixed-Signal) Verification Engineer based in Valencia to join our engineering team. In this role, you will collaborate closely with system architects and analog/digital designers to develop and execute comprehensive verification strategies for state-of-the-art Mixed-Signal SoCs.

Key Responsibilities:

• Drive specification reviews to generate initial verification plans using Vmanager.
• Define verification strategies, including optimal partitioning between DMS and DV, and model versus schematic equivalence.
• Plan and manage resources, schedules, and progress tracking, identifying and addressing potential showstoppers.
• Implement verification plans, run regressions, and track functional and code coverage.
• Verify the accuracy and performance of behavioral models against circuit-level simulations and measurements.
• Perform root-cause analysis and debug issues down to RTL, gate, and schematic levels.
• Maintain and improve functional verification infrastructure, flows, and UVM methodologies.
• Provide technical leadership, mentorship, and support across multi‑site engineering teams.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Telecommunications, Computer Science, or a related field.
• Proven experience in developing validation plans, analyzing test results, and debugging failures at RTL, gate, and schematic levels.
• Strong working knowledge of SystemVerilog/Verilog and UVM.
• Experience setting up, running, and debugging Gate-Level Simulations (GLS).
• Good understanding of DSP techniques and analog schematics.
• Strong problem‑solving, communication, and teamwork skills.
• Professional working proficiency in English (C1 level minimum).
• Valid work authorization for the European Union is required.

Preferred / Bonus Skills:

• Experience with System Modeling or Formal Verification.
• Proficiency in scripting languages such as Python, Make, or Shell.

Additional Information

Diversity is an integral part of our corporate strategy and is anchored as one of our values in the “We are Bosch” mission statement. For us, diversity is reflected in the uniqueness of our associates, their personalities, experiences and perspectives. By including everyone and ensuring equal opportunities we unleash our full potential. We are dedicated to ensuring that our hiring processes are fair, inclusive, and free from bias. We are committed to hiring individuals regardless of culture, generation, race, religion an belief, neurodiversity, gender identity, sexual orientation, or disabilities.