Mixed-Signal Design & Verification Engineer Lead

Monolithic Power Systems, Inc.; Barcelona; On-site; EUR 70,000 - 100,000; Full time

Job summary

Monolithic Power Systems, Inc. is seeking a Mixed-Signal Design & Verification Lead in Barcelona, Spain. This role involves leading the MPS Mixed-Signal Design team and developing frameworks for complex digital and mixed-signal ICs. Candidates should have extensive experience in ASIC design and leadership capabilities.

The ideal applicant will possess solid skills in transistor-level design and strong knowledge of the ASIC development process. In addition, proficiency in industry-standard simulation tools and a collaborative approach are necessary.

Qualifications

• 12+ years experience in ASIC Mixed-Signal design with BSEE or 8+ years with MSEE.
• Strong independence and collaborative skills across teams.
• Solid understanding of ASIC development and silicon processes.

Responsibilities

• Lead and mentor the Mixed-Signal Design Team.
• Supervise project quality metrics and deliverables.
• Engage in Analog and Mixed-Signal Design and validation.

Skills

Leadership skills

Mixed-Signal Design

Transistor-level design

Communication skills

Education

BSEE with 12 years experience or MSEE with 8 years experience

Tools

Spectre

HSPICE

Cadence ADE-L

Cadence ADE-XL

Calibre

ICV

Job description

Job Summary

A Mixed-Signal Design & Verification Lead will lead, train and mentor the MPS Mixed-Signal Design team and will define and lead the development of the Mixed-Signal Design/Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions on devices such as switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for a variety of portable and non-portable markets including notebooks, cell phones, telecom, digital cameras, automobiles and network equipment.

Essential Functions

• Lead, supervise, mentor and train the MPS Mixed-Signal Design Team.
• Supervise multiple projects to meet quality metrics, deliverables and schedules.
• Participate in the Mixed-Signal Design recruitment process.
• Perform Analog and Mixed-Signal Design, Verification and Validation for projects.
• Define and document Analog-Digital Interfaces.
• Model Analog Blocks behaviorally and analyze architectural choices and trade‑offs.
• Define, develop, integrate and verify Analog and Mixed-Signal IP.
• Conduct Analog and/or Digital Mixed-Signal simulations and debugging.
• Assist the Digital Design Team with Timing, I/O and DFT Constraints.
• Support Post‑Silicon Validation and Characterization.
• Maintain close interaction and collaboration with Analog Design, Analog Layout, Digital Design Engineers, Digital Verification, and Digital Physical Engineers.

Qualifications

• BSEE + 12 years of experience; MSEE + 8 years of experience in ASIC Mixed‑Signal design.
• Ability to work independently and collaborate across teams and departments.
• Strong leadership skills to manage multiple projects and a small group of Mixed‑Signal Designers.
• Solid knowledge of the full ASIC development and silicon fabrication process.
• Strong background in transistor‑level and analog/mixed‑signal circuit design.
• Understanding of device mismatches, noise, linearity and other analog effects.
• Knowledge of layout design and best‑practice techniques.
• Experience with simulation tools such as Spectre, HSPICE, or equivalents.
• Proficiency with Cadence circuit design tools like ADE‑L and ADE‑XL.
• Experience running complex simulations such as Monte‑Carlo, noise simulations, and stability analysis.
• Experience running DRC and LVS using Calibre, ICV, etc.
• Experience with Verilog‑AMS mixed-mode simulations and Verilog, System Verilog and Verilog‑A coding for behavioral modeling.
• Knowledge of DFT Techniques such as SCAN, LBIST, ABIST and IDDQ.
• Knowledge of STA and Mixed‑Signal Timing and I/O Constraints for Syn and P&R.
• Excellent written and verbal communication skills and strong teamwork and collaboration.
• Knowledge/Experience with Automotive and ASIL Standards is a plus.

Additional Knowledge

• Power management industry/applications.
• Protocols: I2C, I3C, SPI, USB, PMBUS.
• Experience with GitLab and Cliosoft SOS.

Location

Barcelona, Spain or Portugal

EEO Statement

Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status. A valid disability certificate will be considered a plus as part of our commitment to workplace inclusion and diversity.