Functional Verification Engineer

OPENCHIP & SOFTWARE TECHNOLOGIES; Barcelona; Hybrid; EUR 55,000 - 75,000; Full time

Job summary

Openchip & Software Technologies S.L. in Barcelona is seeking a Functional Verification Engineer to interface with architecture, design, hardware and software teams to ensure top-level system performance.

You will develop verification environments in SystemVerilog/UVM, SystemC/C++, and run verification plans, regressions and debugging; contribute to coverage and methodology improvements. The role is based in Barcelona with hybrid work options.

Qualifications

• Master degree in a relevant field.
• 5+ years of experience in verification of complex SoC/IP.
• Proficiency in SystemVerilog/UVM and SystemC/C++ for verification environments.
• Experience with constrained random, functional coverage, and design debugging.
• Experience in Formal Verification (UPF) and HW-SW co-verification.

Responsibilities

• Read system requirements and architecture documents to develop verification environments in SystemVerilog/UVM/SystemC/C++, including Stimulus, Checkers, Assertions, Trackers, and Coverage.
• Execute verification plans, bring-up DV environments, run regressions, and debug failures with cross-functional teams.
• Create and execute test cases to verify functionality, performance, and robustness in embedded C and SV.
• Perform coverage analysis, bug tracking, and regression testing to ensure verification quality.
• Contribute to verification methodology improvements.

Skills

English proficiency

SystemVerilog/UVM

SystemC/C++

Constrained random

Functional Coverage

Design debugging

Education

Master Degree in relevant field

Tools

SystemVerilog

UVM

SystemC

Embedded C

Bash/Perl/Python scripting

Job description

As a Functional Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.

The Role

Reading and analysing the system requirements and architecture requirement documents. Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage. Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures. Using the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, …). Create and execute testcases to verify the functionality, performance, and robustness in embedded C and SV. Identify, isolate, and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams. Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities. Participation to verification methodology improvements.

Qualifications

• Master Degree in relevant field.
• Min 5 years of experience in relevant field of Verification of complex SoC or IP
• Experience in
• SystemVerilog/UVM
• SystemC/C++
• Experience in Constrained random, Functional Coverage development, design debug.
• Experience in Formal Verification, UPF.
• Experience in HW-SW co-verification and simulation.
• Some previous experience in Firmware based verification is a good to have.
• Some knowledge of scripting languages like Bash/Perl/Python.
• Use of verification management tools.
• Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues.
• Good level of English, both written and spoken is mandatory.

Experience In The Following Are a Plus

• Experience in Firmware-based verification.
• Knowledge in metrics-driven verification.
• Insights of NOC and other Ips or standard peripherals like PCIe, DDR, HBM …

Soft Kills

• Team player, able to work with multiple cultures both on site and remotely.
• Autonomous and flexible is mandatory.

What do we offer?

• Join an innovative team and experience company growth.
• We believe in investing in our employees and providing them with the opportunities they need to grow and develop their careers.
• Enjoy a hybrid work environment.
• We also offer flexible schedule.
• We offer a remuneration that values your experience.
• The position will have the base in Barcelona.

At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.