DFT Engineer - Remote/Barcelona, SoC Test & Yield

Semidynamics; Barcelona; Hybrid; EUR 60,000 - 80,000; Full time

Benefits offered by this job

Barcelona office

WFH 1 day

Work from anywhere

Competitive package

Job summary

Semidynamics is seeking a DFT Engineer to design and implement DFT architectures for complex SoCs and chiplets, collaborating with design, validation, external IP/EDA partners. You will drive testability, yield, and manufacturability across pre-silicon to mass production.

The role requires 4+ years in RTL/SystemVerilog, DFT tools such as Tessent, and hands-on test development across silicon, package, and system levels; Barcelona-based, with a weekly WFH option.

Qualifications

• Bachelor’s, Master’s, or PhD in Computer Science, Electrical Engineering, or a related field.
• 4+ years of related experience.
• Must have - experience with Tessent and SSN methods integrated with leading EDA design flows for advanced technology nodes is a plus.
• Proven experience with multiple tape-outs of high-performance SoCs or SiPs for mass production.
• Strong background in post-silicon test optimization and yield analysis.
• Experience in defining and implementing test strategies for high-volume production.
• Proficiency in RTL and testbench development using SystemVerilog and Verilog.
• Strong scripting skills (Shell, Tcl, Python3).

Responsibilities

• Define and implement DFT architectures to improve testability, debug capabilities, and manufacturability.
• Ensure proper insertion of DFT features such as scan chains, BIST, and JTAG interfaces.
• Optimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield.
• Test Development & Implementation
• Develop and implement test plans and test strategies at silicon, package, and system levels.
• Define and develop automated test solutions for production and characterization.
• Ensure test coverage for all product development stages, from pre-silicon to mass production.
• Guarantee high yield on the final solution while considering chiplet complexities.
• Cross-Functional Collaboration
• Work closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability.
• Collaborate with product management to ensure alignment with customer requirements and timelines.
• Process Improvement & Innovation
• Continuously explore and implement new DFT methodologies and manufacturing processes.
• Lead initiatives for cost reduction, efficiency improvements, and quality enhancements in test and production.

Skills

RTL/Verilog

SystemVerilog

Testbench

Scripting: Shell

Scripting: Tcl

Python

Education

BSc/MSc/PhD in CS/EE

Tools

Tessent

SSN

Job description

Semidynamics is seeking a DFT Engineer to design and implement DFT architectures for complex SoCs and chiplets, collaborating with design, validation, external IP/EDA partners. You will drive testability, yield, and manufacturability across pre-silicon to mass production.

The role requires 4+ years in RTL/SystemVerilog, DFT tools such as Tessent, and hands-on test development across silicon, package, and system levels; Barcelona-based, with a weekly WFH option.