Senior Synthesis & Timing Lead Engineer

Semidynamics; Cataluña; Híbrido; EUR 90.000 - 120.000; Jornada completa

Descripción de la vacante

Semidynamics in Barcelona is seeking an experienced STA & Synthesis Lead Engineer with hands-on RTL-to-gate synthesis, MMMC timing analysis, and SDC constraint development to drive sign-off from RTL through implementation.

You will collaborate with RTL, DFT, and Physical Design teams to optimize PPA, resolve timing bottlenecks, and deliver robust, area-efficient designs in a hybrid work setting (4 days in office, 1 day WFH).

Formación

• Hands-on experience in synthesis and STA.
• Strong MMMC timing analysis and sign-off methods.
• Experience with SDC constraint development and debugging.
• Ability to collaborate with RTL, DFT, and Physical Design teams.

Responsabilidades

• Perform physical-aware RTL-to-gate synthesis and optimize for PPA.
• Develop, review, validate, and debug SDC timing constraints for block-level and top-level designs.
• Execute Static Timing Analysis across MMMC scenarios and sign-off.
• Lead timing closure activities and ECO generation with PD/P&R teams.

Conocimientos

Synthesis & STA

PPA optimization

MMMC timing analysis

SDC constraints

Herramientas

Fusion Compiler

Primetime

Formality

VCLP

Descripción del empleo

Semidynamics in Barcelona is seeking an experienced STA & Synthesis Lead Engineer with hands-on RTL-to-gate synthesis, MMMC timing analysis, and SDC constraint development to drive sign-off from RTL through implementation.

You will collaborate with RTL, DFT, and Physical Design teams to optimize PPA, resolve timing bottlenecks, and deliver robust, area-efficient designs in a hybrid work setting (4 days in office, 1 day WFH).