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GMV is expanding its GNSS-User Segment Navigation team in Castilla-La Mancha, Spain. You will help migrate architecture from Xilinx MPSoC/FPGA to an ASIC solution and contribute to RTL development, verification and ASIC flow with a strong emphasis on accuracy and innovation.
Ideal candidates have a background in digital hardware design and experience with SystemVerilog, UVM and related tools, plus embedded ARM/RISC-V processors and HW/SW partitioning.
ASIC Design Engineer GMV viñuelas, castilla la mancha, Spain
ASIC Design Engineer | Job DetailsAre you looking for an innovative and consolidated place for your professional development? GMV is an experienced technology group and…We are expanding our teams in the GNSS-User Segment Navigation unit to take on projects related to receivers technology.Well get to the point; we'll tell you what's not on the web. If you want to know more about us go to GMV website.
As part of the GMV Receivers team, you will have a key role in projects related to receiver technology, contributing to the development of projects and products with strong involvement in R&D activities. You will participate in migrating an arquitecture currently implemented on Xilinx MPSoC / FPGA to an ASIC solution. Additionally, you will have the opportunity to work on the analysis of the existing design, identification of reusable blocks, adaptation of the hardware architecture, and definition of the ASIC implementation flow.
For this role, we are looking for graduates in Electronic Engineering, Telecommunications, Computer Science, or similar, with a specialization in the field of digital hardware programming.Additionally, we are seeking profiles with knowledge of digital RTL design, FPGA , SoC or MPSoC architectures, internal buses, IP integration, and functional verification; as well as previous experience in ASIC flow and handling simulation and synthesis tools.We will also value previous knowledge of STA, DFT, scan, low-power, UPF, floorplanning or backend; verification with SystemVerilog, UVM, assertions or cocotb; embedded ARM/RISC-V processors and hardware/software partitioning; and experience with Synopsys, Cadence, Siemens EDA, Vivado, or Vitis tools.
Hybrid working model and 8 weeks per year of teleworking outside your usual geographical area.Flexible start and finish times, and intensive working hours Fridays and in summer. Personalized career plan development, training and language learning support. National and international mobility. Do you come from another country? We can offer you a relocation package.Competitive compensation with ongoing reviews, flexible compensation and discount on brands. Wellbeing program: Health, dental and accident insurance; free fruit and coffee, physical, mental and financialhealth training, and much more! In our recruitment processes you will always have telephone and personal contact, face-to-face or online, with our talent acquisition team. In addition, bank transfers and bank cards will never be requested. If you are contacted through any other process, please write to our team at
We promote equal opportunities in recruitment, and we are committed to inclusion and diversity.
If you have any questions please do not hesitate to contact Carolina Barber Caso, in charge of this vacancy.Carolina Barber Caso