Senior Digital IC Designer

IC Resources; München; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

IC Resources in Munich seeks a Senior Digital IC Design Engineer to join a team delivering cutting-edge digital logic designs. You will contribute RTL implementations, timing optimization, and robust verification using Verilog/SystemVerilog.

The role emphasizes collaboration with analog, verification, backend and test teams, plus post-silicon bring-up support to ensure successful silicon validation.

Qualifikationen

• PhD or Master’s in Electrical Engineering with at least 5 years of relevant industry experience.
• Proficiency in Verilog and SystemVerilog.
• Strong digital design fundamentals including clocking, multi-clock logic, CDC, FIFO, FSM.

Aufgaben

• Developing micro-architecture specifications for logic circuits.
• RTL designs using Verilog or SystemVerilog.
• Designing standalone test benches to verify RTL behavior.
• Writing and verifying SystemVerilog Assertions (SVA) for designs.
• Defining timing constraints and clock parameters for synthesis and place-and-route tools.
• Running synthesis tools and resolving timing issues.
• Balancing design trade-offs for timing, area and power.
• Analyzing STA reports using industry-standard tools.
• Collaborating with cross-functional teams including analog, verification, backend, system and test engineers.
• Supporting post-silicon bring-up, validation and debugging activities.

Kenntnisse

Verilog

SystemVerilog

Digital logic

Scripting

STA

Ausbildung

PhD in Electrical Engineering

Master’s in Electrical Engineering

Tools

Genus

Design Compiler

PrimeTime

Jobbeschreibung

Overview

We are seeking a highly skilled and motivated Senior Digital IC Design Engineer to join our team. This role offers the opportunity to tackle unique technical challenges and contribute to the development of cutting-edge digital logic designs. The ideal candidate will possess a strong foundation in digital design and implementation, with a passion for innovation and collaboration. If you are a professional with a proven track record in digital logic design, we encourage you to apply.

Responsibilities

• Developing micro-architecture specifications for logic circuits
• RTL designs using Verilog or SystemVerilog.
• Designing standalone test benches to verify RTL behavior.
• Writing and verifying SystemVerilog Assertions (SVA) for designs.
• Defining timing constraints and clock parameters for synthesis and place-and-route tools.
• Running synthesis tools (e.g., Genus or Design Compiler) and resolving timing issues.
• Balancing design trade-offs, including timing, area, and power optimization.
• Analyzing Static Timing Analysis (STA) reports using industry-standard tools (e.g., Prime Time).
• Collaborating with cross-functional teams, including analog, verification, backend, system, and test engineering teams.
• Supporting post-silicon bring-up, validation, and debugging activities.

Qualifications

• PhD and 3 years or Master’s degree in Electrical Engineering with a minimum of 5 years of relevant industry experience.
• Proficiency in Verilog and SystemVerilog.
• Strong understanding of digital logic design fundamentals, including clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc.
• Experience in mixed-signal digital logic design.
• Basic knowledge of Discrete Time Signal Processing theory, FIR, and IIR filter design.
• Expertise in digital design flow, including RTL design, synthesis, timing constraints, and STA.
• Proficiency in scripting languages such as Perl, Tcl, or Python.