Senior Digital Design Engineer

microTECH Global Limited; München; Vor Ort; EUR 60.000 - 100.000; Vollzeit

Zusammenfassung

microTECH Global Limited in Munich, Germany is seeking a Senior Digital Design Engineer to lead RTL design and verification for advanced digital circuits, collaborating with cross-functional teams.

You will develop micro-architecture specs from PRD, craft Verilog/SystemVerilog RTL, write test benches, SVA assertions, and guide timing constraints and synthesis, ensuring robust digital design flows.

Qualifikationen

• Master’s degree in electrical engineering with 5+ years of industry experience.
• Excellent verbal and written communication skills in English.
• Proficient in Verilog and SystemVerilog.
• Expertise in digital logic design fundamentals (clock dividers, multi-clock designs, CDC, FIFO, FSM).
• Experience in designing mixed-signal digital logic and RTL flow (synthesis, timing constraints, STA).
• Skilled in scripting languages Perl/Tcl/Python.

Aufgaben

• Developing micro-architecture specification of the logic circuit from PRD.
• Developing RTL design from micro-architecture using Verilog/SystemVerilog.
• Creating standalone test benches to verify RTL behavior.
• Writing and verifying SystemVerilog Assertions (SVA).
• Writing timing constraints and clock definitions for synthesis/Place & Route.
• Running industry-standard synthesis tools (Genus/Design Compiler) and fixing timing issues.
• Understanding design trade-offs in timing/area/power.
• Reading STA reports from tools like PrimeTime.
• Cross-functional collaboration with analog, verification, backend, system, and test teams.
• Post-Si bring-up, validation, and debugging.

Kenntnisse

Verilog

SystemVerilog

Digital logic design

RTL design

Perl/Tcl/Python

English fluency

Ausbildung

Master's degree in Electrical Engineering

PhD in electrical/computer engineering

Tools

Genus

Design Compiler

PrimeTime

Jobbeschreibung

Job Title: Senior Digital Design Engineer

Location: Munich, Germany

Job Type: Permanent

Salary: 60K – 100K EUR per annum - Dependant on experience

Responsibilities:

• Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD).
• Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL.
• Developing standalone test benches to verify the RTL behavior.
• Writing and verifying SystemVerilog Assertions (SVA) for a design.
• Writing timing constraints and clock definition for synthesis and place and route tools.
• Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise.
• Understanding various design tradeoffs including timing/area/power and knowing how to improve them.
• Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time).
• Cross-functional interactions and communication with various teams within SiTime including analog, verification, backend, system, and test engineering teams.
• Post-Si bring-up, validation, and debugging.

Qualifications & Requirements (Education must be included):

• Master’s degree in electrical engineering plus 5 years of relevant work experience in the industry.
• Excellent verbal and written communication skills in English.
• Proficient in Verilog and SystemVerilog.
• Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc.
• Experience in designing mixed-signal digital logic.
• Basic understanding of Discrete time Signal Processing theory, FIR, and IIR filter design.
• Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA.
• Skilled in scripting languages Perl/Tcl/Python.

Desired Characteristics & Attributes:

• Ph.D. in electrical/computer engineering plus 3 years of relevant industry experience.
• 2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing.
• 2-5 years of experience in designing Digital Phase-Locked Loops (DPLL).
• Experience in complex FSM design.
• Familiarity with MATLAB, Simulink, or any other high-level modeling tools.
• Experience in low-power digital design flow.
• Basic understanding of the Control Theory.