Sr. Engineer, Digital Design

Sitime-Corporation; München; Vor Ort; EUR 90.000 - 120.000; Vollzeit

Zusammenfassung

SiTime Corporation in Germany seeks a Senior Logic Design Engineer to advance RTL/Verilog/SystemVerilog based designs for MEMS-based timing solutions. You will craft micro-architecture specifications, build RTL and verification test benches, and optimize timing, area, and power with cross-functional teams.

Required are a Master’s in electrical engineering with 5 years’ experience, fluency in English, and strong skills in Verilog/SystemVerilog, DSP basics, and scripting.

Qualifikationen

• Master’s degree in electrical engineering with 5 years in industry required.
• Excellent verbal and written English communication.
• Proficient in Verilog and SystemVerilog.
• Experience with digital logic design fundamentals (clock dividers, multi-clock logic, CDC, FSM).
• Knowledge of DSP basics: FIR/IIR filtering.
• Strong digital design flow experience: RTL, synthesis, timing constraints, STA.
• Scripting: Perl/Tcl/Python.

Aufgaben

• Develop micro-architecture specifications from PRD.
• Create RTL designs in Verilog/SystemVerilog and verify with test benches.
• Write and verify SystemVerilog Assertions (SVA).
• Define timing constraints for synthesis and PnR.
• Run synthesis (Genus/Design Compiler) and fix timing issues.
• Read STA reports and optimize design timing/area/power.
• Collaborate with analog, verification, backend, system, and test teams.
• Post-Si bring-up, validation, and debugging.

Kenntnisse

Verilog

SystemVerilog

RTL design

Synthesis

STA

Perl

Python

Tcl

English

Digital logic

Ausbildung

Master's degree in Electrical Engineering

PhD in Electrical/Computer Engineering

Tools

Genus

Design Compiler

Jobbeschreibung

Job Summary

SiTime Corporation is a precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry. For more information, visitwww.sitime.com .

We at SiTime take pride in being the only company in the market that offers MEMS-based timing solutions. Our MEMS dies are uniquely complemented by our CMOS dies in the same package. We use state-of-the-art analog and digital circuits to achieve very aggressive design specs for our timing solutions. Our precision timing products keep pushing the boundaries of the industry across all dimensions and are by far superior to our competition. This has enabled us to continuously gain market share.

This has been achieved by pushing the innovation boundaries in MEMS and CMOS. Consisting of analog and digital blocks, our CMOS dies present unique technical challenges. The digital portion of our chips has been growing in the past few years and is expected to grow more rapidly in the upcoming years as our functionality and features scale up. To address our unique technical challenges, we are looking for a strong Senior Logic Design Engineer with a solid background in key digital design and implementation areas. It is not necessary to meet all job requirements to be a qualified candidate for the position.

Responsibilities:

• Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD).
• Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL.
• Developing standalone test benches to verify the RTL behavior.
• Writing and verifying SystemVerilog Assertions (SVA) for a design.
• Writing timing constraints and clock definition for synthesis and place and route tools.
• Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise.
• Understanding various design tradeoffs including timing/area/power and knowing how to improve them.
• Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time).
• Cross-functional interactions and communication with various teams within SiTime including analog, verification, backend, system, and test engineering teams.
• Post-Si bring-up, validation, and debugging.

Qualifications & Requirements (Education must be included):

• Master’s degree in electrical engineering plus 5 years of relevant work experience in the industry.
• Excellent verbal and written communication skills in English.
• Proficient in Verilog and SystemVerilog.
• Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc.
• Basic understanding of Discrete time Signal Processing theory, FIR, and IIR filter design.
• Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA.
• Skilled in scripting languages Perl/Tcl/Python.

Desired Characteristics & Attributes:

• Ph.D. in electrical/computer engineering plus 3 years of relevant industry experience.
• 2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing.
• 2-5 years of experience in designing Digital Phase-Locked Loops (DPLL).
• Experience in complex FSM design.
• Familiarity with MATLAB, Simulink, or any other high-level modeling tools.
• Basic understanding of the Control Theory.

The actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

SiTime compensation packages includes base salary, bonus based on achieving your innovation goals and equity.

Learn More about SiTime:

Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.