Digital IC Designer

Intellectual Capital Resources Ltd

Bayern

Vor Ort

EUR 65.000 - 90.000

Vollzeit

14 Tage+
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Zusammenfassung

Intellectual Capital Resources Ltd in Germany seeks a Digital IC Design Engineer to contribute to brain-computer interface chip development. Roles range from junior to senior, based in the EU with right to work in Germany.

You will design digital ICs, optimize power, performance and area, and work with Verilog/SystemVerilog tools across the design flow from RTL to physical design. FPGA implementation experience is a plus.

Qualifikationen

  • A doctoral or master's degree in a relevant field with strong academic performance.
  • Proven silicon-proven digital IC designs and strong RTL/Verilog skills.
  • Expertise across digital design flows from algorithm to RTL and physical design.
  • Experience with PPA optimization for digital designs.
  • Familiarity with Verilog/SystemVerilog and real-number modeling/verification.

Kenntnisse

Digital IC design
RTL design
Verilog/SystemVerilog
PPA optimization

Ausbildung

Master's or PhD in Electrical Engineering, Microelectronics, Physics

Tools

FPGA toolchain

Jobbeschreibung

We are seeking a highly skilled and motivated Digital IC Design Engineer to join our team in developing the next generation of brain-computer interfaces. This role offers the opportunity to contribute to groundbreaking advancements in HealthTech, working on implantable chips that will transform lives and push the limits of innovation. Junior to senior level experience will be considered provided they are based in the EU and a have the pre-existing right to work in Germany.

To be considered for this role you have the following experience:
  • A degree or doctorate in Electrical Engineering, Microelectronics, Physics, or a related field, with outstanding academic performance
  • Silicon-proven designs in digital ICs
  • Excellent knowledge of digital IC design flows, from algorithm to RTL capture and physical design, using industry standard tools
  • PPA (power, performance [timing], area) optimization for digital designs
  • Expertise in Verilog/SystemVerilog, and real-number modeling and verification
  • Experience with FPGA implementation and verification is a plus
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