ASIC Digital Design Verification, Principal Engineer

Synopsys Inc; München; Vor Ort; EUR 60.000 - 90.000; Vollzeit

Zusammenfassung

Synopsys Inc is seeking an enthusiastic ASIC Digital Design Engineer in Munich, Germany. This role focuses on designing verification environments for Interface IP protocols, collaborating with teams to ensure high-quality outputs, and mentoring junior engineers. The ideal candidate should have expertise in digital design, strong communication skills, and a proactive mindset. You will work with cutting-edge technology and contribute to innovations in ASIC design, enhancing the verification processes. The position offers an opportunity to make a significant impact in the field of chip design.

Qualifikationen

• Proficiency in digital design and verification methodologies.
• Experience with developing testbenches using System Verilog and UVM.
• Expertise in advanced verification techniques.
• Familiarity with Python or Perl for automation.

Aufgaben

• Design and implement verification environments for Interface IP protocols.
• Collaborate with design teams to identify and fix bugs.
• Verify complex digital IP with detailed test plans and coverage analysis.
• Mentor junior verification engineers on best practices.
• Conduct design and verification reviews for quality improvement.
• Document design specifications and verification reports.

Kenntnisse

Proficiency in digital design and verification methodologies

Experience with developing testbenches using System Verilog and UVM

Expertise in using advanced verification techniques

Familiarity with scripting languages such as Python or Perl for automation

Excellent problem-solving skills

Attention to detail

Excellent communication skills

Ability to work collaboratively

Proactive and self-motivated attitude

Jobbeschreibung

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

An enthusiastic and detail-oriented ASIC Digital Design Engineer with a passion for cutting-edge technology and a penchant for solving complex problems. You thrive in a collaborative environment and are adept at translating high-level requirements into robust and efficient designs. Your expertise, coupled with your strong understanding of digital design and verification methodologies, makes you an invaluable asset to any project. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges, and delivering innovative solutions. You are proactive, with excellent communication skills that enable you to work effectively with cross-functional teams. Your ability to adapt quickly to new challenges and technologies ensures that you remain at the forefront of industry advancements.

What You’ll Be Doing:

• Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing all tasks related to verifying a complex digital IP, including detailed test plans, functional coverage analysis, and driving coverage closure.
• Mentoring and guiding junior verification engineers in best practices and methodologies.
• Conducting design and verification reviews and providing constructive feedback to improve overall quality and functionality.
• Documenting design specifications, test plans, and verification reports.
• Proficiency in System Verilog, UVM, SVA, and other verification techniques.
• Strong understanding of digital design and verification concepts.
• Excellent problem-solving skills and attention to detail.

The Impact You Will Have:

• Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
• Enhancing the robustness and efficiency of our verification processes and methodologies.
• Contributing to the successful launch of Interface IP products, impacting various industries.
• Driving innovation and excellence within the verification team.
• Improving the overall performance and functionality of Synopsys' IP offerings.
• Fostering a culture of continuous improvement and technical excellence.

What You’ll Need:

• Proficiency in digital design and verification methodologies.
• Experience with developing testbenches using System Verilog and UVM.
• Expertise in using advanced verification techniques.
• Familiarity with scripting languages such as Python or Perl for automation.

Who You Are:

• Detail-oriented with a strong analytical mindset.
• Excellent communicator, able to convey complex technical concepts clearly.
• Collaborative team player who thrives in a dynamic environment.
• Proactive and self-motivated, with a commitment to continuous learning.
• A results-driven professional committed to delivering high-quality work.
• Mentor and leader, capable of guiding and developing junior engineers.

The Team You’ll Be A Part Of:

You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.