Senior AMS IC Designer

IC Resources; München; Vor Ort; EUR 110.000 - 170.000; Vollzeit

Zusammenfassung

IC Resources is seeking a highly skilled Senior AMS IC Design Engineer in Munich to advance precision timing circuits using MEMS technology. You will design analog and mixed-signal circuits, contribute to architectural definitions, and verify at schematic and post-layout levels while accounting for DFT and DFM.

The role involves close collaboration with layout and cross-functional teams to bring up and characterize chips.

Qualifikationen

• MS in Electrical Engineering or PhD with relevant experience.
• Strong CMOS knowledge and noise analysis.
• Experience with PLL, Sigma-Delta ADC, LNA, temperature sensors, filters, high-speed output stages.

Aufgaben

• Design analog and mixed-signal circuits meeting specifications.
• Contribute to architectural definition of designs and chip integration.
• Perform schematic and post-layout verification with DFT/DFM considerations.
• Collaborate with Layout Engineers to validate layouts.
• Participate in chip bring-up, evaluation, and characterization of owned blocks.
• Work cross-functionally with Product, Characterization, Test and Application Engineers.

Kenntnisse

CMOS circuit design

Noise analysis

Schematic design

VerilogA

Ausbildung

Master's degree in Electrical Engineering

PhD in Electrical Engineering (relevant experience)

Tools

Cadence analog design tools

MATLAB

Jobbeschreibung

We are seeking a highly skilled and motivated Senior AMS IC Design Engineer to join an innovative new design team in Munich. In this role, you will contribute to the development of precision timing circuits utilizing cutting-edge MEMS technology.

Responsibilities

• Design analog and mixed-signal circuits that meet architectural requirements and technical specifications
• Contribute to the architectural definition of designs and chip integration
• Perform calculations, design, and verification simulations to ensure building blocks meet specifications at both schematic and post-layout levels, while accounting for DFT and DFM
• Collaborate with Layout Engineers to validate proper layout using best-known methods
• Actively participate in chip bring-up, evaluation, and characterization, with a focus on owned blocks
• Work cross-functionally with Product, Characterization, Test, and Application Engineers to address issues related to owned circuit blocks
• Support additional projects as required by management or evolving business needs

Qualifications

• M.S. in Electrical Engineering or related field with a minimum of 4 years of relevant experience, or Ph.D. in Electrical Engineering with a minimum of 2 years of relevant experience
• Strong academic background with published research projects proven in silicon
• In-depth knowledge of CMOS circuits and noise analysis and experience in schematic design of some of the following: PLL, Sigma Delta ADC, temperature sensors, filters, LNA's, bandgap, high speed output stages
• Proficiency in overseeing circuit layout for critical blocks
• Familiarity with programming languages such as MATLAB and VerilogA
• Proficient in using Cadence analog design tools

This is an exciting opportunity to work on industry-leading technology that powers a wide range of applications. You will have the chance to collaborate with a talented team of engineers and contribute to groundbreaking innovations in precision timing circuits. If you are ready to take your career to the next level, we look forward to hearing from you.

Full job soec on request! To apply, please contact Ane @ IC Resourceswith your CV and a time for an inital call today!