Mixed Signal Design Engineer (DAC/ADC) - Visas Supported

European Tech Recruit; Nordrhein-Westfalen; On-site; EUR 60,000 - 80,000; Full time

Job summary

A technology recruitment agency is seeking a Mixed Signal Design Engineer to join an award-winning semiconductor company in Aachen, North Rhine-Westphalia. The role involves designing innovative converter IPs for various applications. Candidates should have a master's or Ph.D. in Electrical Engineering, along with hands-on experience in mixed-signal IC design, particularly ADC/DAC circuits, and proficiency in Cadence design tools. Strong collaboration skills are essential in this position.

Qualifications

• 3-5 years of relevant experience for Mid-Level, 6+ for Senior-Level.
• Hands-on experience in mixed-signal IC design, particularly ADC/DAC circuits.
• Full-custom analog layout techniques and ability to verify layouts.

Responsibilities

• Develop behavioral models and perform architecture-level trade-off analysis.
• Collaborate closely with layout engineers to ensure layout matching.
• Support silicon bring-up, lab validation, and debugging of first silicon.

Skills

Mixed-signal IC design

Communication skills

Collaboration

Behavioral modeling (Verilog-A, SystemVerilog-AMS)

Analog design fundamentals

Education

M.Sc. or Ph.D. in Electrical Engineering or related field

Tools

Cadence Virtuoso

Spectre

Job description

Mixed Signal Design Engineer (DAC/ADC) – Visas Supported

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A fantastic opportunity for an experienced Mixed Signal Design Engineer to join an award-winning semiconductor company, where you will contribute to innovative converter IPs for use in communications, sensor interfaces, signal processing, and SoC products.

Responsibilities

• Solid understanding of ADC/DAC architectures, performance metrics, design trade‑offs, and criteria for deciding which ADC/DAC designs are suitable for different applications.
• Solid understanding of and experience with building block circuits for measurement sub‑systems such as bandgaps, CMOS bias generators, TIAs, op‑amps, filters, switched‑cap circuits, LDOs, ADCs, etc.
• Extensive hands‑on experience with EDA design tools such as Cadence Virtuoso, preferably with a history of successful Tapeouts.
• Develop behavioral models and perform architecture‑level trade‑off analysis.
• Expertise in techniques for high‑precision circuit design in the presence of large device mismatch and high supply noise.
• Collaborate closely with layout engineers to ensure layout matching and parasitic‑aware design. Experience in C / MATLAB / Verilog modeling.
• Support silicon bring‑up, lab validation, and debugging of first silicon.
• Document design and verification results, and support IP integration into customer products.

Your Profile

• M.Sc. or Ph.D. in Electrical Engineering or related field.
• Hands‑on experience in mixed‑signal IC design, particularly ADC/DAC circuits.
• Strong understanding of analog design fundamentals (noise, matching, linearity, stability).
• Knowledge of system‑level integration and SoC interfacing.
• Proficiency with Cadence design tools, Spectre, and behavioral modeling (Verilog‑A, SystemVerilog‑AMS).
• Full‑custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign‑off.
• Experience with advanced CMOS process nodes.
• Good communication skills and ability to work in a collaborative team environment.

(Mid‑Level: 3‑5 years of relevant experience. – Senior‑Level: 6+ years in related field.)

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Aachen, North Rhine‑Westphalia, Germany