Integrated Circuit Design Verification Engineer

Jobtailor; Deutschland; Vor Ort; EUR 120.000 - 180.000; Vollzeit

Zusammenfassung

Jobtailor in Germany seeks an experienced ASIC Design Verification engineer to join a multi-disciplinary team. You will focus on verification using UVM and SystemVerilog, developing testbenches, and ensuring functional and code coverage across complex ASIC designs.

You will collaborate with digital and analog teams, software and verification engineers, and use Siemens Questa for verification and debugging, while contributing to automated verification flows.

Qualifikationen

• 10+ years of experience in ASIC Design Verification
• Strong knowledge of UVM and SystemVerilog for advanced verification methodologies
• Experience with digital functional simulation and Siemens Questa
• Proficiency in Verilog RTL coding practices
• Experience with scripting in TCL, Make, Perl, Python and Linux

Aufgaben

• Design and verify ASIC blocks as part of a multi-disciplinary team
• Develop UVM-based and assertion-based testbenches and test plans
• Utilize Siemens Questa toolset for verification and debugging
• Specify and configure verification tools and automation

Kenntnisse

UVM-based verification

SystemVerilog

Digital functional simulation

Verilog RTL coding

Scripting & automation

Ausbildung

BSEE

MSEE

Tools

Siemens Questa

TCL

Make

Perl

Python

Shell Scripts

Linux Environment

Jobbeschreibung

• Work as part of a multi-disciplinary team designing display Integrated Circuits for AR
• Work closely with digital design, analog logic, software and verification engineers
• Develop and implement UVM-based and assertion-based testbenches
• Create and execute verification test plans, including functional coverage and code coverage
• Utilize Siemens Questa tool set for verification and debug tasks
• Specify and configure tools and create automation

Requirements

• BSEE or MSEE or relevant years of experience
• 10+ years of experience in ASIC Design Verification
• Strong knowledge of UVM and SystemVerilog for advanced verification methodologies
• Strong knowledge of digital functional simulation, and tools such as Siemens Questa
• Strong knowledge of good Verilog RTL coding practices
• Scripting and automation, such as TCL, Make, Perl, Python and Shell scripts in Linux environment

Hard Skills

• UVM-Based Testbenches
• Assertion-Based Testbenches
• Digital Functional Simulation
• Verilog RTL Coding Practices
• TCL
• Make
• Perl
• Python
• Shell Scripts
• Linux Environment

Certifications & Qualifications

• BSEE
• MSEE