Senior Digital ASIC Design Engineer Verification (m/f/d)

Advantest; Böblingen; Vor Ort; EUR 75.000 - 110.000; Vollzeit

Zusammenfassung

Advantest in Böblingen is seeking a Senior Digital ASIC Design Engineer Verification (m/f/d) to join a global, highly skilled engineering team. You will drive verification of digital and full‑custom modules, translate requirements into robust test plans, and contribute to silicon bring‑up for next‑gen semiconductor testers with end‑to‑end ownership.

Collaborating with system architects, software engineers and product marketing, you will apply RTL knowledge (Verilog/SystemVerilog) and standard

Qualifikationen

• University degree in EE or equivalent.
• Experience in digital design (SOC), ASIC design methodologies and silicon development cycle.
• RTL coding experience in Verilog and SystemVerilog.
• Experience with verification methodologies and concepts.
• Experience with standard digital design simulation tools.
• Basic knowledge of UNIX or Linux and programming languages.
• Strong communication, teamwork and problem-solving skills.
• Proficient in English.

Aufgaben

• Requirements gathering for IP architecture development for CMOS designs.
• Design and RTL coding of digital and full-custom modules.
• Verification on module and chip level with test plans and cases.
• Documentation of implemented functionality.
• Support verification methodology.
• Collaboration with other functions.

Kenntnisse

Digital design

ASIC design methodologies

RTL coding (Verilog & SystemVerilog)

Verification methodologies

Simulation tools

Unix/Linux basics

Programming languages

English language skills

Teamwork

Problem solving

Ausbildung

University degree, Diploma or BS EE

Tools

Verilog

SystemVerilog

Jobbeschreibung

Senior Digital ASIC Design Engineer Verification (m/f/d)

Böblingen

Kennziffer: 8202

Overview

Join a global, highly skilled engineering team at the heart of Advantest's cutting edge IC test solutions. As a Digital ASIC Design Engineer, you will help create the key technologies that enable the next generation of semiconductor testing. You will work on complex mixed signal ASICs used in Advantest's industry leading testers, taking digital modules and subsystems from first concept all the way to silicon in the final system, giving you true end to end ownership. In this role, you will collaborate closely with system architects, software engineers, product marketing, and other engineering disciplines. You will translate requirements into robust tests, solve challenging technical problems, and deliver high quality results on schedule and at scale.

Responsibilities

• Requirements gathering and elicitation for IP Architecture development for CMOS designs
• Design and RTL coding of digital and full-custom modules
• Verification on module and chip level including test plan/cases generation with a focus on chip level
• Documentation of implemented functionality
• Support for verification methodology
• Collaboration with other functions

Qualifications

• University degree, Diploma or BS EE
• Background in digital design (SOC), ASIC design methodologies and silicon development cycle
• Experience in Register Transfer Level (RTL) coding (Verilog and System-Verilog)
• Experience with verification methodologies and concepts
• Experience with standard simulation tools for digital designs
• Basic knowledge about UNIX or Linux environment and using programming languages
• Technical communication, teamwork and problem solving skills
• English language skills