Senior Formal Verification Engineer - Vector Unit

United States Digital Space LLC; Aachen; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

United States Digital Space LLC seeks a Senior Formal Verification Engineer to join one of our clients’ teams in Aachen, Germany. You will own formal verification for vector units, design scalable testbenches, and ensure the mathematical integrity of the vector pipeline.

You will collaborate with RTL and simulation peers, review SVA properties, and drive formal sign-off on high-complexity arithmetic blocks. 5+ years in hardware verification and SystemVerilog fluency required.

Qualifikationen

• Education: B.S./M.S. or Ph.D. in relevant field with practical experience.
• 5+ years of hardware verification experience with formal methods.
• Strong ability to translate counter-examples into actionable bugs.

Aufgaben

• Design and maintain formal testbenches for Vector Unit sub-blocks.
• Verify IEEE-754 floating-point and integer vector arithmetic units.
• Diagnose and resolve proof-convergence issues and state-space explosions.
• Prove conformance to RISC-V Vector Extension specifications.

Kenntnisse

SystemVerilog

SVA (SystemVerilog Assertions)

Formal verification

Python scripting

Debugging

Case-splitting

Word-level models

Tcl/Bash scripting

Ausbildung

B.S./M.S. in Computer Engineering or Electrical Engineering or Computer Science

Ph.D. in formal methods or computer arithmetic (optional)

Tools

Cadence JasperGold/DPV

Synopsys VC Formal

Siemens OneSpin

Jobbeschreibung

At the company, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

• End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
• Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
• Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
• RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
• Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

• Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
• SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Must Have

• Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
• Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
• Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
• Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
• Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
• Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
• Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

• RISC-V Core Verification.
• RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
• Emulation platforms (Veloce, ZeBu).
• Core/Bus interface protocols (e.g., AXI/CHI).

Essential Soft Skills

• An adversarial, gap-seeking mindset — instinctively asks "who actually checks this?" — with a strong umbrella view of the whole core.
• Clear communication across DV, design, and software teams; writes verification plans others can follow.