PMU Analog Layout Design Intern (m/f/d)

Apple; München; On-site; EUR 13,000 - 18,000; Part time

Job summary

Apple is seeking a motivated intern (m/f/d) in Custom Analog Layout in Munich to gain hands-on experience in chip design. You will support our Power Management team in developing analog ICs powering Apple devices, working with layout engineers and circuit designers to learn the full layout and verification flow in modern sub-micron CMOS technologies.

You will gain exposure to transistor-level layout, layout verification tools, floor-planning, and layout techniques for device matching and

Qualifications

• Currently enrolled student in Electrical Engineering, Microelectronics, or a related field.
• Basic knowledge of semiconductor technology / CMOS circuits.
• Analytical mindset, attention to detail, and enjoyment of precise, hands-on work.
• Basic familiarity with Unix/Linux command-line environments.
• English language fluency (both written and verbal).
• Team player with strong communication skills for working across disciplines.

Responsibilities

• Support transistor-level layout of analog circuit blocks under the guidance of experienced colleagues.
• Assist with layout verification (DRC, LVS, PERC, DFM) using Siemens EDA (Calibre).
• Gain insight into block- and top-level floor-planning together with the design team.
• Analyse and document layout results and support design reviews.
• Learn layout techniques for device matching, minimising parasitics, and power routing.

Skills

Analytical mindset

Attention to detail

Team player

English fluency

Education

Electrical Engineering

Microelectronics

Related field

Tools

Cadence Virtuoso

Unix/Linux

Calibre

Job description

Summary

The Silicon Engineering team is looking for a motivated intern (m/f/d) in Custom Analog Layout who wants to gain hands-on experience in chip design. You will support our Power Management team in developing analog ICs that power millions of Apple products around the world. Working closely with experienced layout engineers and circuit designers, you'll get exposure to the full layout and verification flow used in modern sub-micron CMOS technologies.

Description

• Support transistor-level layout of analog circuit blocks under the guidance of experienced colleagues
• Assist with layout verification (DRC, LVS, PERC, DFM) using Siemens EDA (Calibre)
• Gain insight into block- and top-level floor-planning together with the design team
• Analyse and document layout results and support design reviews
• Learn layout techniques for device matching, minimising parasitics, and power routing

Minimum Qualifications

Currently enrolled student (m/f/d) in Electrical Engineering, Microelectronics, or a related fieldBasic knowledge of semiconductor technology / CMOS circuits, e.g. from coursework or projectsAnalytical mindset, attention to detail, and enjoyment of precise, hands-on workBasic familiarity with Unix/Linux command-line environmentsEnglish language fluency (both written and verbal)Team player with strong communication skills for working across disciplines

Preferred Qualifications

Ideally some initial exposure to layout tools such as Cadence Virtuoso or similar full-custom environments