Technical Lead - RTL-to-GDSII Backend Design

Synthara AG; Zürich; Vor Ort; CHF 180.000 - 240.000; Vollzeit

Zusammenfassung

Synthara AG in Zürich seeks an experienced ASIC physical design leader to own end-to-end RTL-to-GDSII flows and build a scalable backend team. You will define methodologies, constraints, and quality metrics while personally de-risking the most challenging blocks.

You will drive tapeouts, floorplanning, P&R, CTS, STA, DFT/MBIST synergy, and CI/CD automation, shaping a flow that delivers reliable, repeatable sign-off.

Qualifikationen

• 10+ years in ASIC physical design.
• 2+ successful tapeouts as block/subsystem owner from synthesis to sign-off.
• Deep expertise in one complete tool chain (Synopsys or Cadence).
• Hands-on power-optimization techniques, including glitch reduction and activity-based power correlation (VCD/SAIF).
• Strong MCMM STA and timing-closure experience.
• Experience with grid planning, IR/EM analysis, and fixes; hierarchical integration (hard-macros, abstracts/LEF).
• UPF/CPF know-how for multi-voltage designs, including power-aware STA and sim.
• Scripting for automation (Tcl, Python) and version control (Git, Perforce).
• Ability to work independently and lead major decisions.

Aufgaben

• Define and maintain RTL-to-GDS flow, including constraint strategy, libraries/PDKs, UPF/CPF, and sign-off checks.
• Run synthesis, floorplan, partitioning, P&R, CTS, routing, extraction, and closure.
• Create predictable PPA targets and tracking; lead timing/power ECOs and correlate pre/post-layout timing.
• Integrate custom macros, SRAMs, and I/O; manage clocking strategy, CDC, and LEF-based integration.
• Own power intent (UPF/CPF), isolation/retention strategies, level shifting, and power-aware STA/simulation.
• Partner with DFT on scan/MBIST insertion and test timing; ensure routes do not compromise test coverage.
• Industrialize the flow with Tcl/Python automation, reproducible configurations, dashboards, and CI/CD for nightly builds.
• Recruit and develop a 5+ engineer backend team; establish sign-off standards and repeatable flow.
• Engage with foundries on PDK updates, antenna/density rules, and reliability guidance.

Kenntnisse

ASIC physical design

Tapeout leadership

Timing closure

MCMM STA

PPA optimization

UPF/CPF

Scripting: Tcl/Python

Version control

Team leadership

Tools

Synopsys tools

Cadence tools

Git/Perforce

Tcl/Python scripting

Jobbeschreibung

Synthara AG in Zürich seeks an experienced ASIC physical design leader to own end-to-end RTL-to-GDSII flows and build a scalable backend team. You will define methodologies, constraints, and quality metrics while personally de-risking the most challenging blocks.

You will drive tapeouts, floorplanning, P&R, CTS, STA, DFT/MBIST synergy, and CI/CD automation, shaping a flow that delivers reliable, repeatable sign-off.