Technical Lead – Physical Design (RTL to GDSII)

Synthara AG; Zürich; Vor Ort; CHF 180.000 - 240.000; Vollzeit

Zusammenfassung

Synthara AG in Zürich seeks an experienced ASIC physical design leader to own end-to-end RTL-to-GDSII flows and build a scalable backend team. You will define methodologies, constraints, and quality metrics while personally de-risking the most challenging blocks.

You will drive tapeouts, floorplanning, P&R, CTS, STA, DFT/MBIST synergy, and CI/CD automation, shaping a flow that delivers reliable, repeatable sign-off.

Qualifikationen

• 10+ years in ASIC physical design.
• 2+ successful tapeouts as block/subsystem owner from synthesis to sign-off.
• Deep expertise in one complete tool chain (Synopsys or Cadence).
• Hands-on power-optimization techniques, including glitch reduction and activity-based power correlation (VCD/SAIF).
• Strong MCMM STA and timing-closure experience.
• Experience with grid planning, IR/EM analysis, and fixes; hierarchical integration (hard-macros, abstracts/LEF).
• UPF/CPF know-how for multi-voltage designs, including power-aware STA and sim.
• Scripting for automation (Tcl, Python) and version control (Git, Perforce).
• Ability to work independently and lead major decisions.

Aufgaben

• Define and maintain RTL-to-GDS flow, including constraint strategy, libraries/PDKs, UPF/CPF, and sign-off checks.
• Run synthesis, floorplan, partitioning, P&R, CTS, routing, extraction, and closure.
• Create predictable PPA targets and tracking; lead timing/power ECOs and correlate pre/post-layout timing.
• Integrate custom macros, SRAMs, and I/O; manage clocking strategy, CDC, and LEF-based integration.
• Own power intent (UPF/CPF), isolation/retention strategies, level shifting, and power-aware STA/simulation.
• Partner with DFT on scan/MBIST insertion and test timing; ensure routes do not compromise test coverage.
• Industrialize the flow with Tcl/Python automation, reproducible configurations, dashboards, and CI/CD for nightly builds.
• Recruit and develop a 5+ engineer backend team; establish sign-off standards and repeatable flow.
• Engage with foundries on PDK updates, antenna/density rules, and reliability guidance.

Kenntnisse

ASIC physical design

Tapeout leadership

Timing closure

MCMM STA

PPA optimization

UPF/CPF

Scripting: Tcl/Python

Version control

Team leadership

Tools

Synopsys tools

Cadence tools

Git/Perforce

Tcl/Python scripting

Jobbeschreibung

Own the end-to-end RTL-to-GDSII implementation for complex IP/SoC subsystems and build the backend team that scales it. You'll define the methodology, constraints, and quality metrics that the team shall adhere to. The team you lead will be responsible for synthesis, floor planning, P&R, clock tree synthesis, multi-corner STA, design for testability, and ECOs to achieve sign-off. You and your team will collaborate tightly not only with our RTL/digital team but also with our full-custom and full-custom layout team, integrating our full-custom design blocks into a digital-on-top mixed ASIC design. This is a hands-on technical leadership role, where you will not only set the flow and lead the team, but also personally de-risk and own the most challenging aspects of the design.

What you’ll do

• Methodology: Define and maintain a modern RTL-to-GDS flow, including constraint strategy, libraries/PDKs, UPF/CPF, and sign-off checks.
• Implementation: Run synthesis, floorplan, partitioning, P&R, CTS, routing, extraction, and closure.
• PPA & quality: Create predictable PPA targets and tracking, lead timing/power ECOs; correlate pre/post-layout timing
• Integration: Integrate custom macros, SRAMs, and I/O, manage clocking strategy, CDC, and hierarchical/hard-macro integration with LEF.
• Low power: Own power intent (UPF/CPF), isolation/retention strategies, level shifting, and power-aware STA/simulation.
• DFT & test hooks: Partner with DFT on scan/MBIST insertion and test timing; ensure routes and constraints don't compromise test coverage or bring-up.
• Automation & CI: Industrialize the flow with Tcl/Python automation, reproducible configurations, metrics dashboards, and CI/CD for nightly builds and regression testing.
• Team: Recruit and performance-develop a 5+ engineer group, set sign-off standards, and ideally establish a flow-based build ensuring repeatability.
• Foundry interface: Engage with foundries on PDK updates, waiver handling, antenna/density rules, and reliability guidance; maintain the flow of information.

Outcomes (first 18 months)

• Tapeout of one or more blocks/subsystems with MCMM (Multi Corner Multi Mode) timing, closed, clean DRC/LVS, and signed-off IR/EM.
• A documented, automated PD flow adopted across projects, with measurable cycle-time and PPA improvements.
• A staffed and functioning backend team with clear ownership areas (timing, power/IR, integration, sign-off) and reliable execution metrics.
• Golden constraints and library strategy (views, corners, derates) with proven correlation (synth - P&R - sign-off) and predictable ECO closure.

Requirements

• 10+ years in ASIC physical design; 2+ successful tapeouts as block/subsystem owner from synthesis to sign-off.
• Deep expertise in one complete tool chain (Synopsys or Cadence)
• Hands-on experience in power-optimization techniques, including glitch reduction and activity-based power correlation (VCD/SAIF).
• Strong MCMM STA and timing-closure experience
• Experience with grid planning, IR/EM analysis, and fixes. Proven floorplanning/partitioning and hierarchical integration (hard-macros, abstracts/LEF, feedthroughs, blockage strategy).
• UPF/CPF know-how for multi-voltage, power-gated designs, including isolation/retention and power-aware STA and sim.
• Scripting for automation (Tcl, Python) and version control (Git, Perforce, or similar)
• Ability to work and lead the activities independently and assume responsibility for major decisions

Nice to have

• DFT exposure (scan planning, test timing, MBIST integration) and formal equivalence workflows.
• Package/board co-design awareness (bump/rail planning, SSO/PI, thermal assumptions).
• Experience at advanced nodes (≤ 7 nm FinFET) with multi-patterning/EUV constraints and variability considerations.
• Familiarity with sign-off for safety-/quality-critical markets (automotive-style reliability targets, waiver governance, documentation rigor).