Senior Physical Design Engineer — Timing & Power Architect

IC Resources; Zürich; Vor Ort; CHF 120.000 - 180.000; Vollzeit

Zusammenfassung

IC Resources is seeking a Senior Physical Design Engineer for a cutting-edge semiconductor client in Zürich, Switzerland. You will own critical physical design tasks across complex IP and SoC designs, ensuring robust silicon on advanced nodes.

You will drive STA, timing ECOs, power-grid planning, IR-drop analysis, and coordinate between synthesis, place-and-route, and sign-off. Strong experience with tapeouts and multi-clock timing is essential.

Qualifikationen

• 5+ years of hands-on physical design experience.
• 2+ successful tapeouts in a performance-focused environment.
• Strong knowledge of STA, multi-clock designs and hierarchical timing closure.
• Hands-on experience with synthesis and P&R on advanced nodes.
• Experience in power-grid design and IR-drop analysis; scripting in Tcl/Python.

Aufgaben

• Own high-quality physical design across IP and SoC blocks.
• Drive STA, timing ECOs, and multi-clock timing closure.
• Plan power-grid design and perform IR-drop analysis.
• Correlate results across synthesis, P&R, and sign-off.

Kenntnisse

STA

Timing closure

IR-drop analysis

Power-grid design

Scripting

Tools

Synthesis tools

P&R flows

STA tooling

Jobbeschreibung

IC Resources is seeking a Senior Physical Design Engineer for a cutting-edge semiconductor client in Zürich, Switzerland. You will own critical physical design tasks across complex IP and SoC designs, ensuring robust silicon on advanced nodes.

You will drive STA, timing ECOs, power-grid planning, IR-drop analysis, and coordinate between synthesis, place-and-route, and sign-off. Strong experience with tapeouts and multi-clock timing is essential.