Senior Timing Closure Engineer for SoC & IP

Synthara AG; Zürich; Vor Ort; CHF 120.000 - 180.000; Vollzeit

Zusammenfassung

Synthara AG in Zürich is seeking an experienced ASIC physical design engineer focused on timing closure. You will drive Static Timing Analysis across corners, shape constraints, and lead ECO loops, partnering with synthesis, P&R, and clock-tree teams to ensure robust clocks and signed-off timing.

You will implement timing constraints, automate checks, and produce repeatable results that reduce ECO cycles. Collaboration with frontend and backend teams is essential to integration of full-custom

Qualifikationen

• 5+ years in ASIC physical design with timing closure.
• Familiarity with STA tools and flows, including clocking and multi-clock designs.
• Hands-on experience with synthesis and place-and-route to drive timing-aware decisions.
• Scripting ability to automate timing analysis and reporting.
• Collaborative approach with front-end, backend, and verification teams.

Aufgaben

• Build, refine, and maintain timing constraints for blocks and top-level designs, including clocks, generated clocks, I/O timing, and exceptions.
• Run STA across corners and modes, close setup/hold, and manage variation and correlation from synthesis to P&R to sign-off.
• Guide clock-tree strategy and debugging; coordinate with P&R on placement, buffering, and routing.
• Lead timing and functional ECOs and land repeatable closure.
• Support gate-level verification needs with timing data and ensure alignment with sign-off views.
• Automate timing checks, report generation, and regressions using scripting; contribute reusable checklists and docs.

Kenntnisse

Timing closure

STA

Cross-domain timing

ECOs

Scripting

Collaborative work

Tools

STA tools

Synthesis

P&R

Clock-tree design

Jobbeschreibung

Synthara AG in Zürich is seeking an experienced ASIC physical design engineer focused on timing closure. You will drive Static Timing Analysis across corners, shape constraints, and lead ECO loops, partnering with synthesis, P&R, and clock-tree teams to ensure robust clocks and signed-off timing.

You will implement timing constraints, automate checks, and produce repeatable results that reduce ECO cycles. Collaboration with frontend and backend teams is essential to integration of full-custom