Senior RTL Design Engineer – Zurich

Sequans Communications Limited; Zürich; Vor Ort; CHF 100.000 - 135.000; Vollzeit

Zusammenfassung

Sequans Communications Limited is hiring for a position within their VLSI team in Zürich. Responsibilities include specifying, designing, and verifying digital blocks for new chipset generations. Candidates should have a degree in computer science or electrical engineering and at least 5 years of experience in ASIC/FPGA development.

Key skills include proficiency in hardware description languages and experience in optimization techniques. The role demands excellent communication skills and the ability to work in a multicultural environment.

Qualifikationen

• At least 5 years of working experience in ASIC and/or FPGA development.
• Experience in multiple clock domains architectures.
• Familiarity with Unix environment.

Aufgaben

• Design (RTL coding) key digital building blocks.
• Requirements analysis and micro architecture definition.
• Contribute to integration, testing and debugging.

Kenntnisse

Hardware description languages (SystemVerilog/Verilog/VHDL)

Optimization techniques for high throughput designs

Front End activities (e.g Lint, CDC, RDC tools)

Programming/scripting (C-Shell, Tcl, Python)

Version control systems (Git, SVN)

Ausbildung

Degree (BSc/MSc/PhD) in computer science or electrical engineering

Tools

Static timing analysis tools

Synthesis tools

Jobbeschreibung

At Sequans, we know that our success depends on our people, so we are always on the lookout for innovators, leaders, and visionaries. Our team is driven by a shared desire to lead in the IoT semiconductor and to push the limits of technology development.

Within the VLSI team, your responsibilities will be to specify, design, implement and verify various digital blocks linked to Sequans’ next chipsets generation. You will work closely with our software, signal processing algorithms, architecture, integration and verification teams and you will be responsible for planning, tracking and reporting activities related to the implementation of your digital blocks.

RESPONSIBILITIES

• Design (RTL coding) of key digital building blocks.
• Requirements analysis and micro architecture (uarch) definition.
• Design optimization in the context of timing, power and area.
• Contribute to top-level integration, testing and debugging.
• Planning, Tracking and reporting of key activities.
• Preparing documentation and technical reports.
• Supporting verification and debugging.
• Third party IPs evaluation.

EXPERIENCE AND SKILLS

• Degree (BSc/MSc/PhD) in computer science, electrical engineering or equivalent studies.
• At least 5 years of working experience in ASIC and/or FPGA development.
• Strong command of hardware description languages (SystemVerilog/Verilog/VHDL).
• Background in optimization techniques for high throughput, low area, low power designs.
• Experience in multiple clock domains architectures.
• Experience in Front End activities (e.g Lint, CDC, RDC tools).
• Familiarity with Unix environment and shell programming/scripting (C-Shell, Tcl, Python).
• Experience in version control systems (Git, SVN).

BONUS SKILLS

• Knowledge of synthesis and static timing analysis tools.
• Knowledge of Place and Route.
• Experience in 3rd-Party IPs integration (NoC, RISC-V, memories, peripherals, etc).
• Exposure to LTE-M/NB-IoT, 4G LTE Cat 1bis, 5G NR.

PROFILE

• Fast learning capabilities, highly motivated, self-starter, autonomous
• Ability to work in a fast moving and multicultural environment
• Excellent written and oral communications skills, fluent English