Senior ASIC Physical Design Lead: RTL to GDSII

Ignite Next GmbH; Zürich; Hybrid; CHF 180.000 - 280.000; Vollzeit

Zusammenfassung

Ignite Next GmbH in Zürich, Switzerland seeks a seniorIC physical design leader to own end-to-end RTL-to-GDSII implementation for complex IP/SoC subsystems. You will define the flow, constraints, and quality metrics, and lead a 5+ engineer backend team through synthesis, floorplanning, P&R, and sign-off to achieve tape-out readiness.

You will collaborate across RTL/digital, full-custom layout, and foundry interfaces, driving automation and robust, repeatable processes for successful developments.

Qualifikationen

• 10+ years in ASIC physical design; 2+ successful tapeouts as block/subsystem owner from synthesis to sign-off.
• Deep expertise in one complete tool chain (Synopsys or Cadence).
• Power-optimization techniques including glitch reduction and activity-based power correlation (VCD/SAIF).
• Strong MCMM STA and timing-closure experience.
• Experienced in floorplanning/partitioning and hierarchical integration (hard-macros, LEF, blocks).
• UPF/CPF know-how for multi-voltage, power-gated designs with isolation/retention and power-aware STA.
• Scripting for automation (Tcl, Python) and version control (Git, Perforce).
• Ability to lead independently and own major design decisions.

Aufgaben

• Define and maintain a modern RTL-to-GDS flow with constraints, libraries/PDKs, UPF/CPF, and sign-off checks.
• Execute synthesis, floorplanning, partitioning, P&R, CTS, routing, extraction, and closure.
• Lead PPA targets and timing/power ECOs; ensure post-layout correlation.
• Integrate custom macros, SRAMs, and I/Os; manage clocking strategy, CDC, and LEF-based integration.
• Own power intent (UPF/CPF) and isolation/retention strategies for power-aware STA.
• Partner with DFT on scan/MBIST insertion and test timing without compromising coverage.
• Industrialize the flow with Tcl/Python automation, CI/CD for nightly builds and regression tests.
• Recruit and develop a 5+ engineer backend team; establish sign-off standards and repeatable flows.
• Engage with foundries on PDK updates, waiver handling, antenna rules, and reliability guidance.

Kenntnisse

Team leadership

RTL-to-GDSII flow ownership

Timing and power optimization

Automation scripting (Tcl/Python)

Cross-functional collaboration

Tools

Synopsys

Cadence

UPF/CPF

LEF

Scripting (Tcl, Python)

Git/Perforce

Jobbeschreibung

Ignite Next GmbH in Zürich, Switzerland seeks a seniorIC physical design leader to own end-to-end RTL-to-GDSII implementation for complex IP/SoC subsystems. You will define the flow, constraints, and quality metrics, and lead a 5+ engineer backend team through synthesis, floorplanning, P&R, and sign-off to achieve tape-out readiness.

You will collaborate across RTL/digital, full-custom layout, and foundry interfaces, driving automation and robust, repeatable processes for successful developments.