Senior ASIC Timing & Physical Design Engineer

Ignite Next GmbH; Zürich; Hybrid; CHF 120.000 - 180.000; Vollzeit

Zusammenfassung

Ignite Next GmbH in Zürich seeks a Backend (Physical Design & Timing) specialist with 5+ years of ASIC experience to own timing closure for complex IP and SoC blocks, integrating our ComputeRAM macros into the digital backend flow.

You will drive Static Timing Analysis across corners, shape constraints, and lead ECO convergence, coordinating with synthesis, P&R, and clock-tree teams to deliver robust clocks and clean sign-off on advanced nodes.

Qualifikationen

• 5+ years in ASIC physical design with timing closure focus.
• Hands-on STA tools experience across clocking and multi-clock designs.
• Experience with synthesis, P&R, and ECOs for timing closure.
• Strong scripting to automate timing analysis and reporting.
• Collaborative with front-end, backend, and verification teams.

Aufgaben

• Build, refine, and maintain timing constraints for blocks and top-level designs, including clocks, generated clocks, I/O timing, and exceptions.
• Run STA across all relevant corners and modes, close setup and hold, and manage variation and correlation from synthesis to P&R to sign-off.
• Guide clock-tree strategy and debugging with clear targets for skew, jitter, and latency; collaborate with P&R on placement, buffering, and routing choices that affect timing.
• Lead timing and functional ECOs, track impacts, and land repeatable closure with minimal overhead.
• Support gate-level verification needs with timing data, and ensure timing/constraints remain consistent with sign-off views.
• Automate timing checks, report generation, and regressions using scripting, and contribute checklists and documentation that others can reuse.

Kenntnisse

STA tooling & timing closure

Scripting for automation

Cross-team collaboration

Clocking & timing expertise

Tools

Synthesis tools

Place-and-Route (P&R)

Static Timing Analysis (STA) tools

Clock-tree synthesis

Jobbeschreibung

Ignite Next GmbH in Zürich seeks a Backend (Physical Design & Timing) specialist with 5+ years of ASIC experience to own timing closure for complex IP and SoC blocks, integrating our ComputeRAM macros into the digital backend flow.

You will drive Static Timing Analysis across corners, shape constraints, and lead ECO convergence, coordinating with synthesis, P&R, and clock-tree teams to deliver robust clocks and clean sign-off on advanced nodes.