Senior Physical Design Engineer

IC Resources; Zürich; Vor Ort; CHF 120.000 - 180.000; Vollzeit

Zusammenfassung

IC Resources is seeking a Senior Physical Design Engineer for a cutting-edge semiconductor client in Zürich, Switzerland. You will own critical physical design tasks across complex IP and SoC designs, ensuring robust silicon on advanced nodes.

You will drive STA, timing ECOs, power-grid planning, IR-drop analysis, and coordinate between synthesis, place-and-route, and sign-off. Strong experience with tapeouts and multi-clock timing is essential.

Qualifikationen

• 5+ years of hands-on physical design experience.
• 2+ successful tapeouts in a performance-focused environment.
• Strong knowledge of STA, multi-clock designs and hierarchical timing closure.
• Hands-on experience with synthesis and P&R on advanced nodes.
• Experience in power-grid design and IR-drop analysis; scripting in Tcl/Python.

Aufgaben

• Own high-quality physical design across IP and SoC blocks.
• Drive STA, timing ECOs, and multi-clock timing closure.
• Plan power-grid design and perform IR-drop analysis.
• Correlate results across synthesis, P&R, and sign-off.

Kenntnisse

STA

Timing closure

IR-drop analysis

Power-grid design

Scripting

Tools

Synthesis tools

P&R flows

STA tooling

Jobbeschreibung

**All applicants must have the right to work in Switzerland**

Our client, a cutting-edge semiconductor company working on next-generation compute architectures, is looking for a Senior Physical Design Engineer to take ownership across complex IP and SoC designs. This is a key technical role focused on high-quality implementation, collaboration, and delivering robust silicon on advanced process nodes.

As a Senior Physical Design Engineer, you’ll be responsible for driving Static Timing Analysis, timing ECOs, power-grid planning, IR-drop analysis, and correlation across synthesis, place-and-route, and sign-off.

Required experience:

• Strong expertise in either timing closure or power/IR-drop sign-off.
• Proven experience in 2+ successful tapeouts
• Solid understanding of STA, multi-clock designs, and hierarchical timing closure.
• Proven hands-on experience with synthesis and P&R flows on advanced nodes.
• Experience in power-grid design, IR-drop analysis
• Proficiency in scripting (Tcl, Python) for flow automation and report generation.