Senior Physical Design Engineer - Timing Closure Expert

Synthara AG; Zürich; On-site; CHF 150,000 - 200,000; Full time

Job summary

Synthara AG in Switzerland seeks an experienced ASIC Physical Design Engineer to own timing closure and sign-off for complex IP and SOC blocks, driving Static Timing Analysis across corners and modes. You will shape constraints, partner with synthesis, P&R, clock-tree, and ECO teams to ensure robust clocks and reliable sign-off on modern nodes.

You will collaborate with our full-custom team to integrate ComputeRAM macros into the digital backend, automate timing checks, and deliver repeatable,

Qualifications

• 5+ years in ASIC physical design with timing closure focus.
• Proficient with STA flows, clocks, multi-clock designs.
• Hands-on with synthesis and place-and-route for timing-aware decisions.
• Scripting to automate timing analysis and reporting.

Responsibilities

• Own timing closure and sign-off for complex IP and SOC blocks.
• Drive STA across corners and modes, shape constraints.
• Collaborate with synthesis, P&R, and clock-tree teams.
• Lead ECO loops to convergence with minimal overhead.
• Automate timing checks and reporting; develop reusable checklists.

Skills

ASIC design

Timing closure

STA tooling

Scripting

ECOs

Clock tree

Tools

Synthesis tools

P&R tools

STA tools

Job description

Synthara AG in Switzerland seeks an experienced ASIC Physical Design Engineer to own timing closure and sign-off for complex IP and SOC blocks, driving Static Timing Analysis across corners and modes. You will shape constraints, partner with synthesis, P&R, clock-tree, and ECO teams to ensure robust clocks and reliable sign-off on modern nodes.

You will collaborate with our full-custom team to integrate ComputeRAM macros into the digital backend, automate timing checks, and deliver repeatable,