Senior Physical Design Lead — RTL-to-GDSII Tapeouts

Beagle; Zürich; On-site; CHF 150,000 - 230,000; Full time

Job summary

Beagle is seeking a Senior ASIC Physical Design Lead to own complex SoC implementation from synthesis through tapeout. You will drive PPA optimization and lead a high-performing team of PD engineers across the flow.

You'll define scalable physical design methodologies, work with RTL, digital design and foundry partners, and ensure robust, power-efficient, high-performance silicon. This role rewards technical leadership and impact.

Qualifications

• 10+ years of ASIC Physical Design experience with at least two tapeouts.
• Proficiency in Synopsys/Cadence toolchains, STA, P&R, CTS, ECOs, and power integrity.
• Experience with hierarchical design, UPF/CPF, PPA optimization and design automation.
• Strong technical leadership and cross-functional collaboration.
• Hands-on RTL-to-GDSII implementation from synthesis to tapeout.
• Ability to define scalable PD methodologies and sign-off flows.

Responsibilities

• Lead RTL-to-GDSII implementation from synthesis to sign-off and tapeout.
• Drive PPA improvements for power, performance, and area.
• Oversee synthesis, floorplanning, placement and routing, CTS, STA and ECO closure.
• Define PD methodologies, constraints, libraries, PDK integration and sign-off flows.
• Manage MCMM timing closure, setup/hold, EM and IR drop.
• Lead integration of analog/mixed-signal blocks, SRAMs, hard macros and IO.
• Implement UPF/CPF-based multi-voltage domains and power management approaches.
• Collaborate with DFT teams on scan insertion and test timing.
• Develop PD automation using Tcl, Python, version control, CI/CD.
• Mentor and lead PD engineers; set standards and milestones.
• Partner with RTL, digital design, full-custom layout and foundry teams.

Skills

RTL to GDSII

Tapeouts

Power integrity

P&R optimization

Leadership

Scripting (Tcl/Python)

Education

Electrical/Electronic Engineering

Tools

Synopsys tools

Cadence tools

STA

P&R

Job description

Beagle is seeking a Senior ASIC Physical Design Lead to own complex SoC implementation from synthesis through tapeout. You will drive PPA optimization and lead a high-performing team of PD engineers across the flow.

You'll define scalable physical design methodologies, work with RTL, digital design and foundry partners, and ensure robust, power-efficient, high-performance silicon. This role rewards technical leadership and impact.