Technical Lead – Physical Design (RTL to GDSII)

Beagle; Zürich; On-site; CHF 150,000 - 230,000; Full time

Job summary

Beagle is seeking a Senior ASIC Physical Design Lead to own complex SoC implementation from synthesis through tapeout. You will drive PPA optimization and lead a high-performing team of PD engineers across the flow.

You'll define scalable physical design methodologies, work with RTL, digital design and foundry partners, and ensure robust, power-efficient, high-performance silicon. This role rewards technical leadership and impact.

Qualifications

• 10+ years of ASIC Physical Design experience with at least two tapeouts.
• Proficiency in Synopsys/Cadence toolchains, STA, P&R, CTS, ECOs, and power integrity.
• Experience with hierarchical design, UPF/CPF, PPA optimization and design automation.
• Strong technical leadership and cross-functional collaboration.
• Hands-on RTL-to-GDSII implementation from synthesis to tapeout.
• Ability to define scalable PD methodologies and sign-off flows.

Responsibilities

• Lead RTL-to-GDSII implementation from synthesis to sign-off and tapeout.
• Drive PPA improvements for power, performance, and area.
• Oversee synthesis, floorplanning, placement and routing, CTS, STA and ECO closure.
• Define PD methodologies, constraints, libraries, PDK integration and sign-off flows.
• Manage MCMM timing closure, setup/hold, EM and IR drop.
• Lead integration of analog/mixed-signal blocks, SRAMs, hard macros and IO.
• Implement UPF/CPF-based multi-voltage domains and power management approaches.
• Collaborate with DFT teams on scan insertion and test timing.
• Develop PD automation using Tcl, Python, version control, CI/CD.
• Mentor and lead PD engineers; set standards and milestones.
• Partner with RTL, digital design, full-custom layout and foundry teams.

Skills

RTL to GDSII

Tapeouts

Power integrity

P&R optimization

Leadership

Scripting (Tcl/Python)

Education

Electrical/Electronic Engineering

Tools

Synopsys tools

Cadence tools

STA

P&R

Job description

Are you an experienced ASIC Physical Design leader ready to take ownership of complex SoC implementation, drive PPA optimisation and lead high-performing engineering teams?

We’re looking for a Senior ASIC Physical Design Lead with deep hands-on RTL-to-GDSII expertise, a strong track record of successful silicon tapeouts, and the technical leadership skills to deliver robust, power-efficient, high-performance semiconductor designs.

This is an opportunity to shape physical design methodologies, solve challenging implementation problems and drive projects from synthesis through to final sign-off and tapeout.

Responsibilities

• Lead RTL-to-GDSII implementation of complex ASICs and SoC subsystems, from synthesis through to sign-off and tapeout.
• Drive power, performance and area improvements, achieving predictable timing closure and high-quality implementation.
• Oversee and contribute hands-on to synthesis, floorplanning, placement and routing (P&R), clock tree synthesis (CTS), static timing analysis (STA), parasitic extraction and engineering change order (ECO) closure.
• Define and maintain scalable physical design methodologies, constraints, technology libraries, PDK integration and sign-off flows.
• Manage multi-corner multi-mode (MCMM) timing closure, setup/hold optimisation, power integrity, IR drop, electromigration (EM) and physical verification.
• Lead the integration of analog/mixed-signal blocks, SRAMs, hard macros and I/O within hierarchical digital-on-top ASIC architectures.
• Implement UPF/CPF-based methodologies, including multi-voltage domains, power gating, isolation, retention and level shifting.
• Define clocking strategies, manage hierarchical integration and address clock domain crossing (CDC) considerations.
• Work closely with DFT teams on scan insertion, MBIST integration, test timing and design-for-test requirements.
• Develop and optimise physical design automation using Tcl, Python, version control and CI/CD methodologies.
• Build, mentor and lead physical design engineers, setting technical standards, ownership models and delivery milestones.
• Partner with RTL, digital design, full-custom layout and foundry teams to resolve implementation challenges and deliver successful tapeouts.

Experience required

• Degree in Electrical/Electronic Engineering, Microelectronics or a related discipline.
• 10+ years of ASIC Physical Design experience and at least two successful tapeouts.
• Strong expertise in Synopsys/Cadence tools, STA, P&R, CTS, ECOs and power integrity.
• Experience with hierarchical design, UPF/CPF, PPA optimisation and design automation.
• Proven technical leadership and cross-functional collaboration skills.
• Excellent analytical, problem-solving, communication and cross-functional collaboration skills.

This role is ideal for a senior physical design engineer who combines deep technical expertise with the ability to influence implementation strategy, develop engineering talent and deliver complex silicon projects.