Senior Physical Design Engineer

Synthara AG; Zürich; On-site; CHF 150,000 - 200,000; Full time

Job summary

Synthara AG in Switzerland seeks an experienced ASIC Physical Design Engineer to own timing closure and sign-off for complex IP and SOC blocks, driving Static Timing Analysis across corners and modes. You will shape constraints, partner with synthesis, P&R, clock-tree, and ECO teams to ensure robust clocks and reliable sign-off on modern nodes.

You will collaborate with our full-custom team to integrate ComputeRAM macros into the digital backend, automate timing checks, and deliver repeatable,

Qualifications

• 5+ years in ASIC physical design with timing closure focus.
• Proficient with STA flows, clocks, multi-clock designs.
• Hands-on with synthesis and place-and-route for timing-aware decisions.
• Scripting to automate timing analysis and reporting.

Responsibilities

• Own timing closure and sign-off for complex IP and SOC blocks.
• Drive STA across corners and modes, shape constraints.
• Collaborate with synthesis, P&R, and clock-tree teams.
• Lead ECO loops to convergence with minimal overhead.
• Automate timing checks and reporting; develop reusable checklists.

Skills

ASIC design

Timing closure

STA tooling

Scripting

ECOs

Clock tree

Tools

Synthesis tools

P&R tools

STA tools

Job description

Seniority:

5+ years relevant industry experience (physical design with a timing focus)

About Synthara

Synthara is a semiconductor company pioneering a new way to compute. Its technology, ComputeRAM®, transforms conventional memory into a computational engine by bringing processing inside memory and removing data bottlenecks that limit modern chips. The result is a leap in performance and efficiency for AI, signal processing, and data‑heavy workloads. ComputeRAM® integrates effortlessly into any hardware and software architecture, from MCUs to advanced accelerators. Behind ComputeRAM®, a dynamic team of both young, talented, and expert senior engineers, looking for new members willing to turn innovation into real performance, shaping the future of efficient, intelligent computing.

About the role

Own timing closure and sign‑off for complex IP and SoC blocks that integrate our full‑custom ComputeRAM® macros. You will drive Static Timing Analysis across corners and modes, shape clean constraints, partner closely with synthesis, place‑and‑route, and clock‑tree teams, and lead ECO loops to convergence. Your work ensures robust clocks, predictable closure, and high‑quality sign‑off on modern nodes. You will work closely with our full‑custom team to integrate our custom IPs into the traditional digital backend flow.

What you’ll do

• Build, refine, and maintain timing constraints for blocks and top‑level designs, including clocks, generated clocks, I/O timing, and exceptions.
• Run STA across all relevant corners and modes, close setup and hold, and manage variation and correlation from synthesis to P&R to sign‑off.
• Guide clock‑tree strategy and debugging with clear targets for skew, jitter, and latency; collaborate with P&R on placement, buffering, and routing choices that affect timing.
• Lead timing and functional ECOs, track impacts, and land repeatable closure with minimal overhead.
• Support gate‑level verification needs with timing data, and ensure timing/constraints remain consistent with sign‑off views.
• Automate timing checks, report generation, and regressions using scripting, and contribute checklists and documentation that others can reuse.

Outcomes (first 18 months)

• Clean timing closure at block and top level across all defined corners and modes, with stable constraints and traceable waivers.
• Documented timing methodology adopted by the team, with measurable reductions in ECO cycles and predictable time‑to‑close.
• Correlated results between synthesis, P&R, and sign‑off, demonstrated by repeatable reports and post‑route margins on critical paths.

Requirements

• 5+ years in ASIC physical design with a strong emphasis on timing closure and sign‑off.
• Familiarity with STA tools and flows, including clocking, cross‑domain concerns, multi‑clock designs, and hierarchical closure.
• Hands‑on experience working with synthesis and place‑and‑route to drive timing‑aware decisions and guide ECOs to closure.
• Scripting ability to automate timing analysis and reporting.
• A collaborative approach with front‑end, backend, and verification teams.

Nice to have

• Experience with power‑aware and low‑power backend.
• Background in scan and test timing, and awareness of verification and physical verification interactions with timing.
• Exposure to advanced nodes and hierarchical sign‑off on large designs.
• Context working on accelerators or memory‑adjacent designs where timing and integration are tightly coupled.