Senior Physical Design Engineer: Tapeouts, STA & P&R

IC Resources; Zürich; On-site; CHF 120,000 - 180,000; Full time

Job summary

Our client, a cutting-edge semiconductor company, is seeking a Senior Physical Design Engineer to own complex IP and SoC implementations on advanced nodes.

You will lead Static Timing Analysis, timing ECOs, power-grid planning, IR-drop analysis, and ensure tight correlation across synthesis, place-and-route, and sign-off. Strong tapeout track record and scripting in Tcl/Python are essential; experience with multi-clock and hierarchical timing is a plus.

Qualifications

• Strong expertise in either timing closure or power/IR-drop sign-off.
• Proven experience in 2+ successful tapeouts.
• Solid understanding of STA, multi-clock designs, and hierarchical timing closure.
• Proven hands-on experience with synthesis and P&R flows on advanced nodes.
• Experience in power-grid design, IR-drop analysis
• Proficiency in scripting (Tcl, Python) for flow automation and report generation.

Responsibilities

• Drive Static Timing Analysis, timing ECOs, and sign-off.
• Lead power-grid planning and IR-drop analysis.
• Ensure correlation across synthesis, place-and-route, and sign-off.

Skills

STA

Timing closure

IR-drop analysis

Tapeout experience

Scripting (Tcl/Python)

Tools

Synthesis

Place & Route (P&R)

Job description

Our client, a cutting-edge semiconductor company, is seeking a Senior Physical Design Engineer to own complex IP and SoC implementations on advanced nodes.

You will lead Static Timing Analysis, timing ECOs, power-grid planning, IR-drop analysis, and ensure tight correlation across synthesis, place-and-route, and sign-off. Strong tapeout track record and scripting in Tcl/Python are essential; experience with multi-clock and hierarchical timing is a plus.