Senior ASIC Timing & Physical Design Engineer

Synthara AG; Zürich; Vor Ort; CHF 100.000 - 130.000; Vollzeit

Zusammenfassung

A semiconductor company based in Zürich seeks an experienced ASIC Physical Design Engineer with a strong emphasis on timing closure and sign-off. Responsibilities include maintaining timing constraints, running Static Timing Analysis, and leading ECOs. The role requires 5+ years of relevant experience, familiarity with STA tools, and scripting capabilities. Join a dynamic team and contribute to high-quality designs in a collaborative environment.

Qualifikationen

• 5+ years in ASIC physical design with a strong emphasis on timing closure and sign-off.
• Familiarity with STA tools and flows, including clocking and multi-clock designs.
• Scripting ability to automate timing analysis and reporting.

Aufgaben

• Build, refine, and maintain timing constraints for designs.
• Run STA across relevant corners and modes, manage timing.
• Lead timing and functional ECOs, track impacts and closures.

Kenntnisse

ASIC physical design

Timing closure and sign-off

Scripting for automation

Collaboration with teams

Tools

STA tools

Synthesis tools

Place-and-route tools

Jobbeschreibung

A semiconductor company based in Zürich seeks an experienced ASIC Physical Design Engineer with a strong emphasis on timing closure and sign-off. Responsibilities include maintaining timing constraints, running Static Timing Analysis, and leading ECOs. The role requires 5+ years of relevant experience, familiarity with STA tools, and scripting capabilities. Join a dynamic team and contribute to high-quality designs in a collaborative environment.