Senior Mixed-Signal Design Engineer for Compute-in-Memory

Ignite Next GmbH; Zürich; Hybrid; CHF 140.000 - 190.000; Vollzeit

Zusammenfassung

Ignite Next GmbH in Zürich, Switzerland, seeks a senior mixed-signal IC designer (MS +4 years or PhD) to drive design, verification, and characterization of custom blocks and memories for ComputeRAM technology.

You will collaborate with digital and layout teams to meet aggressive PPA targets on advanced CMOS nodes, down to 4nm and below, tackling multi-disciplinary timing constraints and IP-quality deliverables.

Qualifikationen

• Hands-on sub-28 nm CMOS experience.
• Quality-oriented approach.
• Proven design ownership in datapath/standard cells, memory/SRAM, data-converters, ultra-low-power, PLLs, or sensor signal chains.
• Clear technical communication; structured planning; cross-functional collaboration with digital/custom/layout.

Aufgaben

• Design & verify mixed-signal circuits/subsystems for ASICs (architecture, transistor-level design, sim, corners/Monte-Carlo, modelling).
• Develop AI-related building blocks as part of our in-memory computing technology.
• Partner across disciplines on interfaces, buses/standard-cell boundaries, and timing/power budgets.
• Contribute to IP-quality specifications, reviews, reusable verification collateral, and documentation for internal reuse and customer delivery.
• Continuously improve flows through scripting/automation (e.g., Python/Tcl) for characterization, report generation, and regressions.

Kenntnisse

Mixed-signal design

Datapath design

Memory/SRAM design

CMOS process 28nm+

Verilog/VHDL

Python scripting

Digital-analog interfaces

Power/Timing analysis

Ausbildung

PhD in Electrical Engineering

MSc in Electrical Engineering

Tools

Cadence Virtuoso

SPICE simulators

Python

Verilog/VHDL

Mentor Graphics

Jobbeschreibung

Ignite Next GmbH in Zürich, Switzerland, seeks a senior mixed-signal IC designer (MS +4 years or PhD) to drive design, verification, and characterization of custom blocks and memories for ComputeRAM technology.

You will collaborate with digital and layout teams to meet aggressive PPA targets on advanced CMOS nodes, down to 4nm and below, tackling multi-disciplinary timing constraints and IP-quality deliverables.