Senior Analog/RF IC Layout Lead: From Floorplan to Finish

IC Resources

Zürich

On-site

CHF 85,000 - 113,000

Full time

14 days+

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Job summary

IC Resources is seeking a Principal Analog/RF IC Layout Engineer to join a client team in France. The role focuses on expert analog and mixed-signal layout, working with circuit designers from floor planning through chip integration and final verification.

You will lead layout activities, manage block and chip-level integration, and ensure layouts meet DRC/LVS/ERC, extraction, and DFM standards. Strong Cadence Virtuoso and Calibre proficiency is essential.

Qualifications

  • 8–10 years of analog/mixed-signal/RF IC layout experience.
  • Strong understanding of high-speed layout and parasitic effects across process technologies.
  • Proficient with Cadence Virtuoso and Calibre for layout verification.

Responsibilities

  • Lead analog and mixed-signal IC layout from floor planning to final integration.
  • Manage chip-level integration of analog, mixed-signal and ASIC blocks.
  • Complete block and top-level verification (DRC, LVS, ERC, extraction, DFM).
  • Collaborate with designers on floor planning, matching, parasitics and critical paths.
  • Coordinate layout activities and schedules with other engineers.
  • Review power/ground routing, electromigration, signal coupling and layout risks.
  • Support final chip finishing and ensure layouts meet performance and manufacturing requirements.

Skills

Analog IC layout
Mixed-signal layout
RF layout
Cadence Virtuoso
Calibre DRC/ERC/LVS
Floor planning
Parasitic management
IR drop analysis
High-speed layout
Communication skills

Tools

Calibre
LVS/DRC verification

Job description

IC Resources is seeking a Principal Analog/RF IC Layout Engineer to join a client team in France. The role focuses on expert analog and mixed-signal layout, working with circuit designers from floor planning through chip integration and final verification.

You will lead layout activities, manage block and chip-level integration, and ensure layouts meet DRC/LVS/ERC, extraction, and DFM standards. Strong Cadence Virtuoso and Calibre proficiency is essential.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Principal Analog IC Layout Engineer
Principal Analog IC Layout Engineer

Intellectual Capital Resources Ltd • Zürich

On-site
CHF 85,000 - 113,000
Senior Analog IC Layout Engineer – Hybrid (FinFET)
Senior Analog IC Layout Engineer – Hybrid (FinFET)

IC Resources • Lausanne

Hybrid
CHF 120,000 - 190,000
Competitive salary
Pension
Private medical cover
+2
Senior IC Layout Engineer — Lead Top-Level Tape-Out
Senior IC Layout Engineer — Lead Top-Level Tape-Out

CSEM • Neuenburg

On-site
CHF 100,000 - 130,000
Senior IC Layout Engineer – FinFET
Senior IC Layout Engineer – FinFET

IC Resources • Lausanne

Hybrid
CHF 120,000 - 190,000
Competitive salary
Pension
Private medical cover
+2
Senior IC Layout Engineer (F/M/D) 100%
Senior IC Layout Engineer (F/M/D) 100%

CSEM • Neuenburg

On-site
CHF 100,000 - 130,000
Senior Custom IC Layout Lead (Analog/Mixed‑Signal)
Senior Custom IC Layout Lead (Analog/Mixed‑Signal)

MACOM • Zürich

On-site
CHF 120,000 - 180,000
Principal Cadence Layout Engineer
Principal Cadence Layout Engineer

MACOM Technology Solutions • Zürich

On-site
CHF 120,000 - 180,000
Senior ASIC Layout Lead - Ultra-Low-Power Mixed-Signal
Senior ASIC Layout Lead - Ultra-Low-Power Mixed-Signal

TalentCloud Group • Lausanne

Hybrid
CHF 120,000 - 180,000
Senior RF/Analog IC Designer for AI Data Centers
Senior RF/Analog IC Designer for AI Data Centers

IC Resources • Zürich

On-site
CHF 150,000 - 190,000
Senior ASIC Physical Layout Engineer
Senior ASIC Physical Layout Engineer

TalentCloud Group • Lausanne

Hybrid
CHF 120,000 - 180,000
Top locations