Principal Analog IC Layout Engineer

IC Resources; Zürich; Vor Ort; CHF 85.000 - 113.000; Vollzeit

Zusammenfassung

IC Resources is seeking a Principal Analog/RF IC Layout Engineer to join a client team in France. The role focuses on expert analog and mixed-signal layout, working with circuit designers from floor planning through chip integration and final verification.

You will lead layout activities, manage block and chip-level integration, and ensure layouts meet DRC/LVS/ERC, extraction, and DFM standards. Strong Cadence Virtuoso and Calibre proficiency is essential.

Qualifikationen

• 8–10 years of analog/mixed-signal/RF IC layout experience.
• Strong understanding of high-speed layout and parasitic effects across process technologies.
• Proficient with Cadence Virtuoso and Calibre for layout verification.

Aufgaben

• Lead analog and mixed-signal IC layout from floor planning to final integration.
• Manage chip-level integration of analog, mixed-signal and ASIC blocks.
• Complete block and top-level verification (DRC, LVS, ERC, extraction, DFM).
• Collaborate with designers on floor planning, matching, parasitics and critical paths.
• Coordinate layout activities and schedules with other engineers.
• Review power/ground routing, electromigration, signal coupling and layout risks.
• Support final chip finishing and ensure layouts meet performance and manufacturing requirements.

Kenntnisse

Analog IC layout

Mixed-signal layout

RF layout

Cadence Virtuoso

Calibre DRC/ERC/LVS

Floor planning

Parasitic management

IR drop analysis

High-speed layout

Communication skills

Tools

Calibre

LVS/DRC verification

Jobbeschreibung

I am recruiting for a Principal Analog/RF IC Layout Engineer to join my client's team in France. I am looking for an experienced IC layout professional with strong custom analog and mixed-signal experience. The Principal Analog/RF IC Layout Engineer will work closely with circuit designers on the layout and verification of complex analog and mixed-signal IP, taking responsibility from floor planning through to chip-level integration and final verification.

Responsibilities

• Lead custom analog and mixed signal IC layout from floor planning through to final integration
• Manage chip level integration of analog, mixed signal and ASIC blocks
• Complete block level and top level verification, including DRC, LVS, ERC, extraction and DFM
• Work with designers on floor planning, matching, parasitic management and critical signal paths
• Coordinate layout activities and schedules with other layout engineers
• Review power and ground routing, electromigration, signal coupling and other layout related risks
• Support final chip finishing and ensure layouts meet performance and manufacturing requirements

Requirements

• Around 8 to 10 years of analog, mixed-signal, or RF IC layout experience
• Strong understanding of high speed layout and parasitic effects across different process technologies
• Experience with Cadence Virtuoso
• Strong ability to interpret Calibre DRC, ERC and LVS results
• Good understanding of IR drop, RC delay, electromigration and chip finishing
• Experience with floor planning and area estimation
• Strong communication skills and the ability to work closely with circuit designers
• FinFET experience is beneficial but not essential
• High-speed BiCMOS layout experience would be advantageous

The role can be based anywhere in France, but candidates must already have the right to work in France, as no sponsorship is available.