Senior IC Layout Engineer — Lead Top-Level Tape-Out

CSEM; Neuenburg; On-site; CHF 100,000 - 130,000; Full time

Job summary

A technology-based company in Switzerland is seeking an experienced IC Layout Engineer with over 10 years in Analog/RF design. This role focuses on delivering innovative IC layouts for CMOS projects and requires expertise in Cadence tools. Responsibilities include executing layout tasks, leading verification processes, and driving best practices in ultra-low-power designs. Strong communication skills in English, with knowledge of French or German as an asset, are preferred. Join a team committed to high-quality IC designs and innovations in technology.

Qualifications

• 10+ years’ experience as an Analog/RF IC Layout Engineer (nanometer CMOS).
• Strong hands-on experience leading top-level activities for mixed-signal ASICs.
• Strong understanding of state-of-the-art techniques for layout implementation.

Responsibilities

• Execute IC layout tasks and ensure on-time, first-pass-quality tape-out readiness.
• Lead chip finishing, verification, version control, and documentation.
• Participate actively in projects to ensure smooth IC layout execution.

Skills

Analog/RF IC Layout Engineering

Cadence Virtuoso

Siemens Calibre

Mixed-signal ASICs

GDS Submission

Education

Education in Electronics

Tools

Cadence Virtuoso XL

Calibre DRC/LVS

Job description

A technology-based company in Switzerland is seeking an experienced IC Layout Engineer with over 10 years in Analog/RF design. This role focuses on delivering innovative IC layouts for CMOS projects and requires expertise in Cadence tools. Responsibilities include executing layout tasks, leading verification processes, and driving best practices in ultra-low-power designs. Strong communication skills in English, with knowledge of French or German as an asset, are preferred. Join a team committed to high-quality IC designs and innovations in technology.