Senior ASIC Physical Layout Engineer

TalentCloud Group; Lausanne; Hybrid; CHF 120.000 - 180.000; Vollzeit

Zusammenfassung

TalentCloud Group in Lausanne area is seeking a Senior ASIC Physical Layout Engineer to lead the layout of advanced mixed-signal ASICs within a multidisciplinary IC design team. You will drive top-level integration, floorplanning and tape-out readiness in a trusted Swiss tech environment.

The role emphasizes collaborating with analog, RF, digital and system designers, resolving LVS/DRC challenges, and shaping layout methodologies for ultra-low-power SoCs and imaging/RF platforms.

Qualifikationen

• Experience delivering full-chip or top-level IC layout.
• Proficient in Cadence Virtuoso (XL).
• Experience with mixed-signal, analog and RF ASICs.
• Knowledge of advanced CMOS technologies.
• Proven tape-out experience.
• Ability to resolve LVS/top-level integration challenges.

Aufgaben

• Lead top-level physical layout integration for advanced mixed-signal ASICs.
• Drive floorplanning, chip finishing and physical verification through to successful tape-out.
• Resolve complex DRC/LVS/ERC challenges across advanced CMOS technologies.
• Collaborate closely with Analog, RF, Digital and System Designers.
• Contribute to ultra-low-power SoCs, imaging devices and advanced RF technologies.
• Help shape physical design methodologies and layout best practices.

Kenntnisse

Full-chip layout

Top-level layout

Mixed-signal ASICs

Analog ASICs

RF ASICs

LVS resolution

Tape-out experience

Tools

Cadence Virtuoso XL

Jobbeschreibung

About the job Senior ASIC Physical Layout Engineer

Senior ASIC Physical Layout Engineer

Location: Lausanne Area / Western Switzerland (Flexible working culture)

Permanent Position

Are you an experienced Layout Engineer looking to work on cutting-edge mixed-signal ASICs that push the boundaries of ultra-low-power technology?

I'm currently supporting a highly respected Swiss technology organization in their search for a Senior ASIC Physical Layout Engineer to join an experienced multidisciplinary IC design team developing next-generation semiconductor solutions.

This is an opportunity to work somewhere that combines the technical challenges of advanced R&D with the stability and long-term vision of an established organization.

What you will be working on

• Lead top-level physical layout integration for advanced mixed-signal ASICs
• Drive floorplanning, chip finishing and physical verification through to successful tape-out
• Solve complex DRC/LVS/ERC challenges across advanced CMOS technologies
• Collaborate closely with Analog, RF, Digital and System Designers
• Contribute to ultra-low-power SoCs, imaging devices and advanced RF technologies
• Help shape physical design methodologies and layout best practices

What we're looking for:

• Strong experience delivering full-chip or top-level IC layout
• Expertise with Cadence Virtuoso (Virtuoso XL)
• Experience with mixed-signal, Analog and/or RF ASICs
• Knowledge of advanced CMOS technologies
• Proven experience supporting successful tape-outs
• Experience resolving complex LVS issues and top-level integration is highly valued

Nice to have:

• Ultra-Low Power (ULP) design
• Advanced process nodes
• RF layout optimization

Why consider this opportunity?

• Work on genuinely innovative semiconductor technology
• Join an internationally recognized Swiss engineering organization
• Collaborative, highly technical environment
• Opportunity to influence future IC development