Senior IC Layout Engineer – FinFET

IC Resources; Lausanne; Hybrid; CHF 120,000 - 190,000; Full time

Benefits offered by this job

Competitive salary

Pension

Private medical cover

Visa sponsorship

Relocation support

Job summary

IC Resources seeks a Senior IC Layout Engineer to join their semiconductor team in Lausanne. The role offers hybrid working, with 3 days per week in the office, and focuses on analog layout and physical verification for high-speed designs.

You will develop custom analog layouts, work on multi-Gigabit SerDes and memory interfaces, apply advanced layout techniques, and use Cadence Virtuoso, Calibre and PVS. Visa sponsorship and relocation support are available where required.

Qualifications

• Experience in custom analog IC layouts for circuits, blocks, and IP.
• Background in high-speed or RF circuit design is highly beneficial.
• Familiarity with process nodes such as 28nm, 16nm and 7nm is desirable.
• Strong emphasis on matching, parasitic reduction, power distribution and ESD.

Responsibilities

• Develop custom analog layouts for circuits, blocks and IP.
• Work on high speed and high frequency circuits including amplifiers, PLLs, DLLs, oscillators and data converters.
• Apply layout techniques for matching, parasitic reduction, power distribution and ESD.
• Support full chip layout, integration and physical verification activities.
• Perform DRC, LVS, parasitic extraction, EM and IR drop analysis.
• Collaborate with teams across advanced process technologies including 28nm, 16nm and 7nm.

Skills

Analog IC Layout

High-speed design

Physical verification

Parasitic extraction

DRC/LVS

Tools

Cadence Virtuoso

Calibre

PVS

Job description

I am recruiting for a Senior IC Layout Engineer to join my client’s growing semiconductor team in Lausanne. The role offers hybrid working, with 3 days per week in the office.

The Senior IC Layout Engineer will be responsible for custom layout and physical verification of analog circuits, blocks and IP used in advanced high speed semiconductor designs, including multi Gigabit SerDes and memory interfaces.

There is also scope to take ownership of wider chip layout activities and progress into a more senior technical position.

Key responsibilities:

• Develop custom analog layouts for circuits, blocks and IP
• Work on high speed and high frequency circuits including amplifiers, PLLs, DLLs, oscillators, buffers, regulators and data converters
• Apply layout techniques for matching, parasitic reduction, power distribution and ESD
• Support full chip layout, integration and physical verification activities
• Perform DRC, LVS, parasitic extraction, EM and IR drop analysis
• Work with advanced process technologies including 28nm, 16nm and 7nm
• Use industry standard tools such as Cadence Virtuoso, Calibre and PVS

My client is looking for an experienced Analog IC Layout Engineer. High speed experience would be advantageous, but is not essential if you have strong experience with complex analog or high frequency designs.

The package includes a competitive salary, pension, private medical cover, visa sponsorship and relocation support where required.