Senior Custom IC Layout Lead (Analog/Mixed‑Signal)

MACOM; Zürich; On-site; CHF 120,000 - 180,000; Full time

Job summary

MACOM seeks an experienced layout engineer to collaborate with the design team on layout and verification of custom analog/mixed-signal IPs in our advanced semiconductor environment. You will lead full-custom IC layout, floor planning, and top-level integration, perform extraction, DRC/LVS/DFM checks, and coordinate with IP layout engineers to deliver robust, high-performance chips.

Strong communication with circuit designers and attention to parasitics, IR drop, and electromigration are

Qualifications

• High-speed analog/mixed-signal layout experience required.
• Strong understanding of parasitics, IR drop, and electromigration.
• Ability to floor plan and estimate area for IC blocks.
• Excellent communication with circuit designers and other layout engineers.
• Bachelor degree in Engineering or equivalent.

Responsibilities

• Layout and verify custom analog/mixed-signal IPs with design team.
• Lead full-custom IC layout design and floor planning for blocks.
• Verify layout with extraction, DRC, LVS, and DFM checks.
• Plan layout schedule and coordinate with IP layout engineers.
• Collaborate on floor planning with designers for top-level integration.
• Review layout for power/ground routing, electromigration, and signal coupling.

Skills

High-speed layout design

Parasitics understanding

IR drop analysis

Floor planning

Team collaboration

Cadence scripting

CADENCE Virtuoso

CALIBRE DRC/LVS interpretation

Education

Bachelor degree in Engineering

Tools

Cadence Virtuoso

CALIBRE

Job description

MACOM seeks an experienced layout engineer to collaborate with the design team on layout and verification of custom analog/mixed-signal IPs in our advanced semiconductor environment. You will lead full-custom IC layout, floor planning, and top-level integration, perform extraction, DRC/LVS/DFM checks, and coordinate with IP layout engineers to deliver robust, high-performance chips.

Strong communication with circuit designers and attention to parasitics, IR drop, and electromigration are