Agentic System-Level Hardware Design Intern

InternHunt; Zürich; On-site; CHF 20,000 - 31,000; Full time

Job summary

Huawei's Zurich Research Center, Switzerland, invites a Research Intern to develop an agentic system-level hardware design flow. You will guide LLM-based agents from a structured specification through RTL and gate-level layouts, applying open-source tools to evaluate each step.

You will work on system-level designs such as RISC-V processors, vector units, accelerators and SoCs, developing verification methodologies and contributing to patents and papers.

Qualifications

• Master/PhD in a relevant field or pursuing this level with strong fundamentals.
• Solid understanding of computer architecture and SoC design.
• Experience with RTL design and Python; familiarity with Verilator and open-source flows.

Responsibilities

• Build and extend agentic workflows from specification to routed layout.
• Apply workflows to RISC-V processors, vector units, accelerators and SoCs.
• Develop verification methodologies; ensure trustworthy results.
• Read papers from DAC/ISCA/MLCAD and reproduce baselines.
• Perform experiments and contribute to patents and research papers.

Skills

Computer architecture

SoC design

Verilog/SystemVerilog

Python

LLM integration

Education

Masters/PhD in Electrical Engineering, Computer Engineering, Computer Science or related field

Tools

Verilator

Yosys

OpenROAD

Chisel

Amaranth

CIRCT/MLIR

Job description

Huawei's Zurich Research Center, Switzerland, invites a Research Intern to develop an agentic system-level hardware design flow. You will guide LLM-based agents from a structured specification through RTL and gate-level layouts, applying open-source tools to evaluate each step.

You will work on system-level designs such as RISC-V processors, vector units, accelerators and SoCs, developing verification methodologies and contributing to patents and papers.