Research Intern: Agentic System-Level Hardware Design

InternHunt; Zürich; On-site; CHF 20,000 - 31,000; Full time

Job summary

Huawei's Zurich Research Center, Switzerland, invites a Research Intern to develop an agentic system-level hardware design flow. You will guide LLM-based agents from a structured specification through RTL and gate-level layouts, applying open-source tools to evaluate each step.

You will work on system-level designs such as RISC-V processors, vector units, accelerators and SoCs, developing verification methodologies and contributing to patents and papers.

Qualifications

• Master/PhD in a relevant field or pursuing this level with strong fundamentals.
• Solid understanding of computer architecture and SoC design.
• Experience with RTL design and Python; familiarity with Verilator and open-source flows.

Responsibilities

• Build and extend agentic workflows from specification to routed layout.
• Apply workflows to RISC-V processors, vector units, accelerators and SoCs.
• Develop verification methodologies; ensure trustworthy results.
• Read papers from DAC/ISCA/MLCAD and reproduce baselines.
• Perform experiments and contribute to patents and research papers.

Skills

Computer architecture

SoC design

Verilog/SystemVerilog

Python

LLM integration

Education

Masters/PhD in Electrical Engineering, Computer Engineering, Computer Science or related field

Tools

Verilator

Yosys

OpenROAD

Chisel

Amaranth

CIRCT/MLIR

Job description

Research Intern: Agentic System-Level Hardware Design

2026-10-03

Role Description

Our CompanyHuawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships, we have established leading end-to-end capabilities and strengths across the carrier networks, enterprise, consumer, and cloud computing fields. Our products and solutions have been deployed in over 170 countries serving more than one third of the world’s population.

Our Research CenterWith 20+ sites across Europe and 1500 researchers, Huawei’s European Research Institute (ERI) oversees fundamental and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. Huawei’s ERI includes the Zurich Research Center (ZRC), located in Zurich, Switzerland. A major element of ZRC is a rapidly growing research laboratory focused on fundamental research in the area of computing systems (new hardware, new software, new algorithms).

The research work of the lab will be carried out not only by Huawei’s internal research staff but also by our academic research partners in universities across Europe. The lab will provide an open research environment where academics will be encouraged to visit and work on fundamental long-term research alongside Huawei staff in an environment that, like the best universities and research institutes, is open and conducive to such world-leading scientific work.

For our Computing Systems Laboratory in Zürich, we are currently looking for an outstanding Research Intern in agentic system-level hardware design. As a key member of our motivated and multicultural team, you will help build an agentic design flow in which LLM-based agents carry a hardware design from a structured, machine-checkable specification all the way down to a routed layout. You will apply it to system-level designs such as RISC-V processors, vector units, accelerators and SoCs, evaluate every step with open-source tools (Verilator, Yosys, OpenROAD), and develop the verification methodology that makes the agents' results trustworthy.

Your Responsibilities

• Build and extend agentic engineering workflows in which LLM-based agents carry a hardware design from a structured, machine-checkable specification all the way to a routed layout: implementation, verification harness, RTL, gate netlist and GDS.
• Apply these workflows to system-level designs (RISC-V processors, vector units, accelerators and SoCs with their memory maps, register blocks and firmware) and evaluate the results at every stage with simulation, formal equivalence checking, synthesis and place-and-route in open-source flows (Yosys, OpenROAD).
• Develop the verification methodology that keeps agents honest: golden and architectural reference models, differential testing, coverage of specification requirements, and reporting of what each stage established and what it did not.
• Read and analyze research papers from EDA, computer architecture and LLM-for-hardware venues (DAC, ICCAD, MLCAD, ISCA, MICRO, etc.) and reproduce state-of-the-art results as baselines.
• Perform experiments, gather insights, contribute to patents and research papers.

Your background

• Enrolled in a Masters/PhD program or completed Masters in Electrical Engineering, Computer Engineering, Computer Science or a related field.
• Solid understanding of computer architecture and SoC design (e.g., RISC-V processors, caches and memory systems, interconnects, accelerators).
• Experience in RTL design (Verilog/SystemVerilog) and Python, with RTL simulation (e.g., Verilator) and digital implementation flows (e.g., Yosys, OpenROAD or commercial equivalents). Experience with hardware construction languages or compiler-based flows (e.g., Chisel, Amaranth, CIRCT/MLIR) is a plus.
• Hands-on experience building with LLMs (agentic coding tools, tool use, context engineering, evaluation of agent output) is a plus.
• Excellent written and verbal communication skills with a proven ability to present complex technical information clearly and concisely to a variety of audiences. Collaborative work style with the ability to work in a multicultural environment.

If you are interested in gaining practical experience while working with the newest technologies and create solutions which enrich people’s life, we are the right company for you. You will be part of a multicultural team and rapidly growing environment - write the future together with us!

To be considered for this role, applicants must be either Swiss citizens, EU-nationals or are eligible to live and work in Switzerland.

Due to regulations non-EU/EFTA citizens must provide a certificate from the university stating that an internship is mandatory as part of the application documents.

We will only consider candidates whose profile and qualifications meet our requirements.