Senior Verification Engineer - SV/UVM & Formal

TekWissen LLC; Markham; Hybrid; CAD 120,000 - 180,000; Part time

Job summary

TekWissen Group is seeking a Verification Engineer V in Markham, Ontario, to join the Display IP team. You will define, develop, and execute verification solutions for complex IP and SoC designs, partnering with architects, RTL designers, firmware, software, and validation teams to ensure first-pass silicon success.

The ideal candidate has 8-10+ years of ASIC/SoC verification experience and strong SystemVerilog/UVM skills, with a track record of developing verification plans, coverage models,

Qualifications

• 8-10+ years of experience in ASIC, IP, or SoC verification.
• Strong expertise in SystemVerilog, UVM, and constrained‑random verification methodologies.
• Proven experience developing verification plans, functional coverage models, and coverage closure.
• Hands‑on experience with formal verification methodologies and industry-standard formal verification tools.
• Strong understanding of assertion‑based verification (SVA) and formal property development.
• Experience creating reusable verification environments, verification IP, and verification infrastructure.
• Solid understanding of digital design concepts, computer architecture, and hardware verification methodologies.
• Experience with simulation, regression management, coverage analysis, and debug tools.

Responsibilities

• Define and execute comprehensive verification strategies for complex IP and subsystem designs.
• Develop verification plans based on architecture and design specifications.
• Design, implement, and maintain scalable SystemVerilog/UVM testbenches and reusable verification components.
• Create directed and constrained-random test scenarios to validate functionality, performance, and robustness.
• Develop functional coverage plans and coverage models, and drive coverage closure.
• Define verification signoff criteria using simulation, functional coverage, assertion coverage, and formal verification metrics.
• Apply formal verification methodologies including property checking, assertion development, protocol verification, and design correctness analysis.
• Develop and maintain assertion-based verification (SVA) infrastructure and verification content.
• Perform debugging and root-cause analysis of simulation, formal verification, and silicon issues.
• Collaborate closely with architects, RTL designers, firmware, software, and validation teams throughout the product lifecycle.
• Analyze verification metrics and recommend improvements to verification quality and efficiency.
• Contribute to verification methodology development, automation, and continuous process improvement.

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline

Master's degree preferred

Tools

SystemVerilog/UVM

Formal verification tools

SVA

Coverage-driven verification

Job description

TekWissen Group is seeking a Verification Engineer V in Markham, Ontario, to join the Display IP team. You will define, develop, and execute verification solutions for complex IP and SoC designs, partnering with architects, RTL designers, firmware, software, and validation teams to ensure first-pass silicon success.

The ideal candidate has 8-10+ years of ASIC/SoC verification experience and strong SystemVerilog/UVM skills, with a track record of developing verification plans, coverage models,