Senior ASIC Verification Engineer – SystemVerilog/UVM

Kibbi Technologies Inc.; Ottawa; On-site; CAD 90,000 - 135,000; Full time

Job summary

TSMC Design Technology Canada Inc. (TDTC) in Kanata, Ottawa, is seeking a Digital Verification Engineer to validate digital circuit implementations and develop test benches.

You will work closely with design teams to enable robust functional verification and prepare manufacturing/tester patterns, debugging issues as needed. The role requires 5–10 years of experience in digital verification and expertise in SystemVerilog, UVM, and EDA tools.

Qualifications

• Master’s or PhD in electrical/computer engineering.
• 5–10 years of industry experience in digital verification.
• Experience writing and debugging test benches; proficiency in SystemVerilog, UVM, assertions, and verification methodologies.
• Unix/Linux experience; scripting languages.
• Familiarity with EDA tools such as Synopsys VCS or Cadence Incisive; verification planning and coverage.
• Strong problem-solving and communication skills; team or independent work capability.

Responsibilities

• Validate digital circuit implementations and develop test benches.
• Perform functional verification and produce manufacturing/tester patterns; debug failing tests.
• Contribute to customization of verification methodologies and improve EDA capabilities.

Skills

SystemVerilog

UVM

Assertions

Debugging

Unix/Linux

Scripting

Digital verification

Education

Master’s / PhD in electrical/computer engineering

Tools

Synopsys VCS

Cadence Incisive

Job description

TSMC Design Technology Canada Inc. (TDTC) in Kanata, Ottawa, is seeking a Digital Verification Engineer to validate digital circuit implementations and develop test benches.

You will work closely with design teams to enable robust functional verification and prepare manufacturing/tester patterns, debugging issues as needed. The role requires 5–10 years of experience in digital verification and expertise in SystemVerilog, UVM, and EDA tools.