IP Verification Engineer — Hybrid FPGA/ASIC Innovator

Advanced Micro Devices; Markham; Hybrid; CAD 110,000 - 150,000; Full time

Job summary

AMD in Markham, Ontario is seeking a Verification Engineer in the AECG Group to verify FPGA/ASIC IP, collaborate with architecture, IP design, PD, and product engineers for first pass silicon success.

You will write UVM-based testbenches, develop test plans, and run regressions while maintaining strong collaboration across sites and time zones. Hybrid work model with ongoing learning opportunities.

Qualifications

• Proficient in IP level ASIC verification.
• Expert in Verilog, System Verilog, Object Oriented programming.
• Expert in developing UVM based verification frameworks and testbenches.
• Scripting and automation of verification processes and flows.
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process.
• Good Computer Architecture, systems knowledge.
• Comfortable in python / perl and editing / maintaining scripts.
• Exposure to leadership or mentorship is an asset.
• Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out.
• Experience with PCIe, CXL, NVMe or ethernet protocols.
• Strong communication skills and the ability to work independently as well as in a cross-site team environment.

Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
• Build the directed and random verification tests
• Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

Skills

Verilog

SystemVerilog

UVM

Python

Perl

PCIe

CXL

NVMe

OO programming

Education

Bachelor's or Master's in Computer or Electrical Engineering

Tools

UVM-based verification frameworks

Job description

AMD in Markham, Ontario is seeking a Verification Engineer in the AECG Group to verify FPGA/ASIC IP, collaborate with architecture, IP design, PD, and product engineers for first pass silicon success.

You will write UVM-based testbenches, develop test plans, and run regressions while maintaining strong collaboration across sites and time zones. Hybrid work model with ongoing learning opportunities.