Verification Engineer V

TekWissen LLC; Markham; Hybrid; CAD 120,000 - 180,000; Part time

Job summary

TekWissen Group is seeking a Verification Engineer V in Markham, Ontario, to join the Display IP team. You will define, develop, and execute verification solutions for complex IP and SoC designs, partnering with architects, RTL designers, firmware, software, and validation teams to ensure first-pass silicon success.

The ideal candidate has 8-10+ years of ASIC/SoC verification experience and strong SystemVerilog/UVM skills, with a track record of developing verification plans, coverage models,

Qualifications

• 8-10+ years of experience in ASIC, IP, or SoC verification.
• Strong expertise in SystemVerilog, UVM, and constrained‑random verification methodologies.
• Proven experience developing verification plans, functional coverage models, and coverage closure.
• Hands‑on experience with formal verification methodologies and industry-standard formal verification tools.
• Strong understanding of assertion‑based verification (SVA) and formal property development.
• Experience creating reusable verification environments, verification IP, and verification infrastructure.
• Solid understanding of digital design concepts, computer architecture, and hardware verification methodologies.
• Experience with simulation, regression management, coverage analysis, and debug tools.

Responsibilities

• Define and execute comprehensive verification strategies for complex IP and subsystem designs.
• Develop verification plans based on architecture and design specifications.
• Design, implement, and maintain scalable SystemVerilog/UVM testbenches and reusable verification components.
• Create directed and constrained-random test scenarios to validate functionality, performance, and robustness.
• Develop functional coverage plans and coverage models, and drive coverage closure.
• Define verification signoff criteria using simulation, functional coverage, assertion coverage, and formal verification metrics.
• Apply formal verification methodologies including property checking, assertion development, protocol verification, and design correctness analysis.
• Develop and maintain assertion-based verification (SVA) infrastructure and verification content.
• Perform debugging and root-cause analysis of simulation, formal verification, and silicon issues.
• Collaborate closely with architects, RTL designers, firmware, software, and validation teams throughout the product lifecycle.
• Analyze verification metrics and recommend improvements to verification quality and efficiency.
• Contribute to verification methodology development, automation, and continuous process improvement.

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline

Master's degree preferred

Tools

SystemVerilog/UVM

Formal verification tools

SVA

Coverage-driven verification

Job description

Overview:

TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Austin, that develops computer processors and related technologies for business and consumer markets. Global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.

Job Title: Verification Engineer V

Duration: 8 Months

Location: Markham, ON

Job Type: Temporary Assignment

Work Type: Onsite/Hybrid

Job Description:

The Role

• Join Display IP team at AMD that is building industry-leading semiconductor products and technologies. As a Verification Engineer 5, you will play a key role in defining, developing, and executing Client verification solutions for complex Display IP and SoC designs.


• You will work closely with architects, design engineers, software teams, and program managers to ensure first-pass silicon success and deliver high-quality products to market.


• The ideal candidate is passionate about verification methodologies, possesses strong expertise in SystemVerilog/UVM-based verification environments, and has hands‑on experience with formal verification, functional coverage planning, and coverage‑driven verification.


• This individual will thrive in a collaborative environment and enjoy solving complex technical challenges across all phases of product development.

Key Responsibilities

• Define and execute comprehensive verification strategies for complex IP and subsystem designs.


• Develop verification plans based on architecture and design specifications.


• Design, implement, and maintain scalable SystemVerilog/UVM testbenches and reusable verification components.


• Create directed and constrained-random test scenarios to validate functionality, performance, and robustness.


• Develop functional coverage plans and coverage models, and drive coverage closure.


• Define verification signoff criteria using simulation, functional coverage, assertion coverage, and formal verification metrics.


• Apply formal verification methodologies including property checking, assertion development, protocol verification, and design correctness analysis.


• Develop and maintain assertion-based verification (SVA) infrastructure and verification content.


• Perform debugging and root-cause analysis of simulation, formal verification, and silicon issues.


• Collaborate closely with architects, RTL designers, firmware, software, and validation teams throughout the product lifecycle.


• Analyze verification metrics and recommend improvements to verification quality and efficiency.


• Contribute to verification methodology development, automation, and continuous process improvement.

Preferred Experience

• 8-10+ years of experience in ASIC, IP, or SoC verification.


• Strong expertise in SystemVerilog, UVM, and constrained‑random verification methodologies.


• Proven experience developing verification plans, functional coverage models, coverage-driven verification strategies, and coverage closure.


• Hands‑on experience with formal verification methodologies and industry-standard formal verification tools.


• Strong understanding of assertion‑based verification (SVA) and formal property development.


• Experience creating reusable verification environments, verification IP, and verification infrastructure.


• Solid understanding of digital design concepts, computer architecture, and hardware verification methodologies.


• Experience with simulation, regression management, coverage analysis, and debug tools.


• Experience working through multiple successful silicon product cycles.


• Strong communication and collaboration skills.

Preferred Technical Skills

• Experience in one or more of the following areas is considered an asset:


• Display IP and display subsystem verification


• Formal verification and assertion-based verification (ABV)


• Functional coverage architecture and coverage closure methodologies


• Graphics, multimedia, and video processing pipelines


• Display interfaces and protocols including DisplayPort, eDP, HDMI, and MIPI


• High-speed interfaces and protocols


• Memory subsystem verification

Academic Credentials

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.


• Master's degree preferred.

What You'll Bring

• Strong problem-solving and analytical skills.


• Ability to work independently and drive technical initiatives.


• Excellent verbal and written communication skills.


• Experience leading verification efforts from planning through signoff.


• Commitment to engineering excellence and product quality.


• Passion to learn and adopt emerging technologies, including AI-assisted engineering tools, to enhance development efficiency and innovation.

TekWissen Group is an equal opportunity employer supporting workforce diversity.