Lead ASIC Verification Engineer: Digital IP & UVM Expert

Synopsys, Inc.; Markham; On-site; CAD 100,000 - 160,000; Full time

Job summary

Synopsys, Inc. in Ontario, Canada, is seeking an enthusiastic ASIC Digital Design Verification Engineer to design and implement verification environments for Interface IP protocols, collaborate with design and architecture teams, and drive coverage and bug fixes.

You will mentor junior verification engineers, conduct design and verification reviews, document specifications and test plans, and apply SystemVerilog, UVM, SVA, and scripting skills to deliver high-quality silicon.

Qualifications

• Experience in ASIC digital verification with Interface IP protocols.
• Strong knowledge of verification methodologies and tools.

Responsibilities

• Design and implement verification environments to verify Interface IP protocols.
• Collaborate with design and architecture teams to identify and fix bugs.
• Perform test plans, functional coverage analysis, and drive coverage closure for complex IP.
• Mentor and guide junior verification engineers in best practices.
• Conduct design and verification reviews and provide constructive feedback.
• Document design specifications, test plans, and verification reports.
• Proficiency in SystemVerilog, UVM, SVA, and other verification techniques.
• Strong understanding of digital design and verification concepts.

Skills

SystemVerilog

UVM

SVA

Digital verification

Tools

Python

Perl

Job description

Synopsys, Inc. in Ontario, Canada, is seeking an enthusiastic ASIC Digital Design Verification Engineer to design and implement verification environments for Interface IP protocols, collaborate with design and architecture teams, and drive coverage and bug fixes.

You will mentor junior verification engineers, conduct design and verification reviews, document specifications and test plans, and apply SystemVerilog, UVM, SVA, and scripting skills to deliver high-quality silicon.