Senior ASIC Verification Engineer – SystemVerilog & UVM

Synopsys Inc; Ottawa; On-site; CAD 90,000 - 140,000; Full time

Job summary

Synopsys Inc in Ottawa is seeking an experienced ASIC Digital Verification Engineer with a strong background in SystemVerilog and UVM to verify complex ASIC designs, including next-gen HBM products.

You will develop verification plans, debug testbenches, automate flows with Python or Perl, and contribute to design reviews. Join a collaborative team delivering high‑quality silicon and advancing verification methodologies.

Qualifications

• BSEE or MSEE with 6+ years of digital design and verification experience
• Strong SystemVerilog and UVM skills with debugging expertise
• Proficient in Python or Perl for automation and workflow improvements
• Ability to work independently and in cross-functional teams

Responsibilities

• Develop and execute verification plans for complex ASIC designs, focusing on next-generation HBM products, while writing and maintaining robust testcases using SystemVerilog and UVM
• Debug testbench and design issues, collaborate closely with design and mixed-signal engineering teams, and help drive issue resolution across the verification flow
• Automate verification flows and processes using scripting languages such as Python or Perl to improve efficiency, coverage, and productivity
• Contribute to design, architecture, and code reviews while documenting verification results, sharing best practices, and supporting team knowledge growth
• Documenting verification results, methodologies, and lessons learned to support knowledge sharing and process improvement.

Skills

SystemVerilog

UVM

Digital design

Debugging

Testbench

Education

BSEE or MSEE

Tools

Python

Perl

Job description

Synopsys Inc in Ottawa is seeking an experienced ASIC Digital Verification Engineer with a strong background in SystemVerilog and UVM to verify complex ASIC designs, including next-gen HBM products.

You will develop verification plans, debug testbenches, automate flows with Python or Perl, and contribute to design reviews. Join a collaborative team delivering high‑quality silicon and advancing verification methodologies.