Front-End ASIC Verification Engineer – UVM Expert

AMD; Ottawa; Hybrid; CAD 90,000 - 130,000; Full time

Benefits offered by this job

Hybrid work model

AMD benefits at a glance

Job summary

AMD is hiring in Ottawa/Markham (hybrid) for a front-end verification engineer. You will work with architecture, IP design, and product engineers to drive first-pass silicon success and robust verification. The role demands strong UVM, SystemVerilog, and RTL debugging skills across Linux/Windows environments.

You will build directed and random tests, craft testbench architectures, and liaise with project managers to coordinate release schedules. Experience with AI-assisted tools is a plus.

Qualifications

• Proven IP level ASIC verification experience.
• Expert in UVM-based verification environments and SystemVerilog.
• Strong debugging of RTL using simulation tools.

Responsibilities

• Collaborate with architects, hardware/firmware engineers to verify new features.
• Build test plans considering interactions with hardware, firmware, and software drivers.

Skills

IP level ASIC verification

RTL debugging

UVM concepts

SystemVerilog

UVM testbenches

Linux & Windows

verification frameworks

automation workflows

AI tools

leadership/mentorship

Networking protocols

Education

Bachelor's or Master's in Computer/Electrical Engineering or CS

Tools

Linux

Windows

Job description

AMD is hiring in Ottawa/Markham (hybrid) for a front-end verification engineer. You will work with architecture, IP design, and product engineers to drive first-pass silicon success and robust verification. The role demands strong UVM, SystemVerilog, and RTL debugging skills across Linux/Windows environments.

You will build directed and random tests, craft testbench architectures, and liaise with project managers to coordinate release schedules. Experience with AI-assisted tools is a plus.