Senior Pre-Silicon Signoff Lead - SerDes & PCIe

Synopsys Inc

Mississauga

On-site

CAD 120,000 - 160,000

Full time

4 days ago

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Job summary

Synopsys Inc. is seeking an senior engineer to lead verification and modeling for high‑speed SerDes IP. You will collaborate across analog, digital, and hardware teams to drive simulation plans, coverage metrics, and sign‑off artifacts.

You will mentor junior engineers and help shape next‑gen connectivity solutions for data centers and enterprise networks. You will develop robust verification strategies, review progress with cross‑site teams, and optimize regression plans for FW releases,

Qualifications

MSc or PhD in Electrical/Computer Engineering with 10+ years of industry experience.
Deep expertise in high-speed protocols—PCIe and Ethernet.
Proficiency in SystemVerilog, UVM/OVM, and assertion-based verification, coverage closure.
Strong scripting/programming: Python, TCL, Perl, C/C++.

Responsibilities

Collaborate with analog, digital, and hardware teams to ensure holistic design and verification coverage.
Develop and maintain comprehensive simulation and verification plans for IP, aligning with reliability and performance targets.
Review execution against verification plans through regular meetings with multiple verification teams.
Establish, monitoring, and reporting on key verification metrics such as functional, code, and assertion coverage.
Coordinate with Firmware & Algorithms Lead and Digital FW Developers to develop hardware regression plans for FW releases.
Deliver high‑quality verification collateral including test plans, test cases, coverage reports, and sign‑off documentation.