Senior SerDes Analog Design & Silicon Correlation Lead

Synopsys, Inc.; Mississauga; On-site; CAD 150,000 - 200,000; Full time

Job summary

Synopsys, Inc. is seeking a visionary analog designer specializing in high-speed SerDes to own macro design across TX, RX, CDR, and clock paths. You will translate standards into robust circuits, balance power and performance, and lead verification strategies.

Collaboration with validation, layout, and modeling teams will shape next-generation IP products. The role demands silicon-proven experience and strong modeling skills, with opportunities to mentor junior engineers and influence design

Qualifications

• MSc with 8+ years or PhD with 6+ years in SerDes/high-speed analog design.
• Silicon-proven TX, RX, and clock-path circuits in SerDes architectures.
• Experience with analog behavioral modeling and device modeling concepts.

Responsibilities

• Own the design and implementation of analog macros for SerDes IP across the TX, RX, CDR, and clock paths.
• Interpret SerDes standards and architecture documents to develop detailed macro specifications.
• Optimize circuits for power, area, and performance, and oversee layout to minimize parasitics and variation impacts.
• Propose and execute verification strategies using advanced simulators, including corner and Monte Carlo analyses.
• Collaborate with digital RTL engineers on calibration, adaptation, and control algorithms for your circuits.
• Define the sim-to-silicon correlation plan for your macros and specify measurement conditions.
• Build and refine models including extracted parasitics and channel/S-parameter models to align simulation with silicon.
• Root-cause gaps between simulation and silicon back to circuit, layout, or device models.
• Partner with validation to guide test plans and interpret data, feeding fixes into the design revision.
• Mentor a small group of analog designers and present results for reviews.

Skills

Transistor-level design

Verilog-A modeling

SPICE simulators

S-parameter modeling

Python/MATLAB scripting

Education

MSc with 8+ years or PhD with 6+ years in SerDes/high-speed analog design

Tools

Verilog-A

SPICE tools

EDA tools

Parasitic extraction

Job description

Synopsys, Inc. is seeking a visionary analog designer specializing in high-speed SerDes to own macro design across TX, RX, CDR, and clock paths. You will translate standards into robust circuits, balance power and performance, and lead verification strategies.

Collaboration with validation, layout, and modeling teams will shape next-generation IP products. The role demands silicon-proven experience and strong modeling skills, with opportunities to mentor junior engineers and influence design